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Design >> Analog Design >> Common Mode Feedback Contorl
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Message started by Ricky Chen on Oct 29th, 2011, 11:31pm

Title: Common Mode Feedback Contorl
Post by Ricky Chen on Oct 29th, 2011, 11:31pm

Dear friends,

I have attached the file containing two CMFB Networks.

One controls a fraction of the Bias current while the Other controls the entire bias current.

Which one is better ? and why ?

-Ricky

Title: Re: Common Mode Feedback Contorl
Post by raja.cedt on Oct 30th, 2011, 12:26am

hello,
there is no diference. Both are same.

Thanks,
Raj.

Title: Re: Common Mode Feedback Contorl
Post by rajkumar palwai on Oct 30th, 2011, 1:16am

Hi Ricky,
The CMFB loop gain of the 1st fig is lower, because gm7 would be smaller compared to that of 2nd fig. By varying the M7 size, u can play with the phase margin of the CMFB loop and thus can adjust for the best CM settling. Also u can adjust the CM loop stability.

But, Fig2 will have more cmfb loop gain and the error in the final settled Common mode value will be less.

-rajkumar


Title: Re: Common Mode Feedback Contorl
Post by raja.cedt on Oct 30th, 2011, 1:30am

hello rajkumar,
you are correct, you are saying with in the first fig you have less current through m7 so less gm compared to 2nd fig, but gm can be varied by current m7 size as well, what i mean to say is to get desired gm no need to put some fixed current correct me if am worng?.

Infact some people say if cmfb doesn't work due to some reason still you get some bias  current through fixeed current.


Thanks,
raj.

Title: Re: Common Mode Feedback Contorl
Post by yvkrishna on Oct 30th, 2011, 2:35am

Hi,

I agree with rajkumar,
we often end up with difficulty in stabilizing the common-mode loop ( though this case looks simple) because not many device parameters  in the signal path are in control to tweak and stabilise this CM loop to get a clean common mode settling response.

Having said that it all depends on the application - how much error OR slowness  we can tolerate in this CM loop.

@Ricky
you can refer Paul Gray's  book for this topic.



Thanks,
yvkrishna


Title: Re: Common Mode Feedback Contorl
Post by rajkumar palwai on Oct 30th, 2011, 5:51am

Hi Raja,
Yes, the gm7 can also be reduced by just reducing its size. But then voltage headroom required to be in saturation (while passing the entire tail current)  will increase and that may hurt. So people typically put a parallel current source and reduce the current through M7.

-rajkumar

Title: Re: Common Mode Feedback Contorl
Post by Ricky Chen on Oct 30th, 2011, 6:26am

Ya it is related to the transient response (settling time) of the circuit.
That is what I was suspecting.

@ raja.cedt

You can change the size of m7 to have desired gm.
However for swing reason one desires to have current source and M7 to have same overdrive so gm/Id for M7 is fixed by the Diff-Amp ckt design.
So to reduce gm of M7 one is left with no option other than to reduce the current of M7

-Ricky


rajkumar palwai wrote on Oct 30th, 2011, 1:16am:
Hi Ricky,
The CMFB loop gain of the 1st fig is lower, because gm7 would be smaller compared to that of 2nd fig. By varying the M7 size, u can play with the phase margin of the CMFB loop and thus can adjust for the best CM settling. Also u can adjust the CM loop stability.

But, Fig2 will have more cmfb loop gain and the error in the final settled Common mode value will be less.

-rajkumar


Title: Re: Common Mode Feedback Contorl
Post by loose-electron on Oct 30th, 2011, 4:50pm

No DC bias at the common mode feedback current point?
What's missing here?

Title: Re: Common Mode Feedback Contorl
Post by Ricky Chen on Oct 31st, 2011, 12:50am


loose-electron wrote on Oct 30th, 2011, 4:50pm:
No DC bias at the common mode feedback current point?
What's missing here?


There is DC f/b.. Please Look at the circuit carefully !!!

Title: Re: Common Mode Feedback Contorl
Post by rajkumar palwai on Oct 31st, 2011, 2:36am

Hi Ricky,
There is no DC path at the gate of M7. If u simply connect the circuit like that feedback doesnot work.
-rajkumar

Title: Re: Common Mode Feedback Contorl
Post by Ricky Chen on Oct 31st, 2011, 8:04am


rajkumar palwai wrote on Oct 31st, 2011, 2:36am:
Hi Ricky,
There is no DC path at the gate of M7. If u simply connect the circuit like that feedback doesnot work.
-rajkumar


There is DC path.
If you kick one side of the open CAP the other end will also get the same kick.

By the way what do you mean by DC path ??

Title: Re: Common Mode Feedback Contorl
Post by wave on Oct 31st, 2011, 1:42pm

Arg!  I'm seeing several incorrect statements today.

Loose E is correct.  
You need Resistors in parallel with the Caps for a DC sense point and DC feedback.

Raja - there IS a difference.  Without a constant bias, it may never startup.  If your DC bias point (broken already) is at a place where Loopgain = 0, you have no CMFB regulation.

:D
Wave

Title: Re: Common Mode Feedback Contorl
Post by loose-electron on Oct 31st, 2011, 3:36pm

LOL!

:D

Title: Re: Common Mode Feedback Contorl
Post by Ricky Chen on Oct 31st, 2011, 11:58pm


wave wrote on Oct 31st, 2011, 1:42pm:
Arg!  I'm seeing several incorrect statements today.

Loose E is correct.  
You need Resistors in parallel with the Caps for a DC sense point and DC feedback.

Raja - there IS a difference.  Without a constant bias, it may never startup.  If your DC bias point (broken already) is at a place where Loopgain = 0, you have no CMFB regulation.

:D
Wave


OK !! So your statement is without resisitor one can NOT sense CM voltage then how things work in SWITCH CAP  CMFB circuit.
By the way the above circuits are the snapshot of one state of SWITCH CAP sense circuit

One thing to mention, even if you give constant current source bias CMFB start-up will still exist if you solely consider only the CKT shown above !!

For your information, there is no difference between a resistive divider (R1 & R2) and a CAPCACITIVE Voltage divider (provided you have control on the initial condition of the CAPs which generally happens in CAP-CMFB circuit).
For Res case Vout=Vin[R2/(R1+R2)] & for CAP case Vout =Vin[C1/(C1+C2)]

!!! :D

Title: Re: Common Mode Feedback Contorl
Post by Praveen K on Nov 1st, 2011, 12:43am

Hi wave,

why are saying the circuit on right will not start up?

won't the current sources M3 and M4 rise X & Y nodes initially and then later get stabilized with M7 in action.

k.praveen

Title: Re: Common Mode Feedback Contorl
Post by rajkumar palwai on Nov 1st, 2011, 4:15am

Praveen,
any leakage path at the gate of M7 will take the steady state node voltage to the extremes eventually and hence the circuit doesn't work.

Title: Re: Common Mode Feedback Contorl
Post by Ricky Chen on Nov 1st, 2011, 4:22am


rajkumar palwai wrote on Nov 1st, 2011, 4:15am:
Praveen,
any leakage path at the gate of M7 will take the steady state node voltage to the extremes eventually and hence the circuit doesn't work.


Rajkumar,

That is why there is a refresh cycle in Switch cap CMFB circuits.
The circuit by the way is the snap-shot of one state of Switch cap CMFB circuit. So DC -ve f/B does EXIST in the above circuit !!

Title: Re: Common Mode Feedback Contorl
Post by rajkumar palwai on Nov 1st, 2011, 4:23am

I mean, at the steady state the average value of the M7 gate voltage would be either '0' or 'vdd' depending on whether the leakage to gnd is strong or leakage to vdd is strong.

U can simulate a simple example case. Put 2 caps in series and give 2 transient signals at the 2 ends. Then connect a big resistor (eg:1e12) at the centre node to gnd/vdd to model the leakage and see the o/p waveforms.

Title: Re: Common Mode Feedback Contorl
Post by rajkumar palwai on Nov 1st, 2011, 4:25am

Ricky,
yaa. it wil work in switch cap cmfb ckts, where we periodically refresh the charge.

But i thought praveen was asking about the DC cap feedback circuit and expalining that.

Title: Re: Common Mode Feedback Contorl
Post by Ricky Chen on Nov 1st, 2011, 4:28am


rajkumar palwai wrote on Nov 1st, 2011, 4:23am:
I mean, at the steady state the average value of the M7 gate voltage would be either '0' or 'vdd' depending on whether the leakage to gnd is strong or leakage to vdd is strong.

U can simulate a simple example case. Put 2 caps in series and give 2 transient signals at the 2 ends. Then connect a big resistor (eg:1e12) at the centre node to gnd/vdd to model the leakage and see the o/p waveforms.


You did NOT understand what I mean to say.
What do you think the leakage impedance will be ?? Will it be such that it will leak the sizable amount of charge from the CAP before the refresh cycle ??

if that you think, then probably switch-CAP circuit would NOT have existed !!

:D

Title: Re: Common Mode Feedback Contorl
Post by rajkumar palwai on Nov 1st, 2011, 6:59am

Ricky,
I do know how a switched cap CMFB works and i designed pipelined ADC's using that.

In my previous post i was just explaining a case when there is no refresh cycle at-all i.e when u connect the fdbk caps just like that and dont refresh them for ever.

I hope u understand.

Title: Re: Common Mode Feedback Contorl
Post by loose-electron on Nov 1st, 2011, 3:53pm


Ricky Chen wrote on Oct 31st, 2011, 11:58pm:
SWITCH CAP  CMFB circuit.
By the way the above circuits are the snapshot of one state of SWITCH CAP sense circuit


None of us can read minds.
You never said anything before about this.
Please define your probably correctly in the
future, and do not assume we have the capability
read your mind from the other side of the planet.

My mind reading capabilities are limited to under a 300km range.
:D

Title: Re: Common Mode Feedback Contorl
Post by raja.cedt on Nov 2nd, 2011, 12:59am

hello wave,
how does current source solve start up problem here?

Thanks,
raj.

Title: Re: Common Mode Feedback Contorl
Post by Ricky Chen on Nov 2nd, 2011, 2:10am


loose-electron wrote on Nov 1st, 2011, 3:53pm:

Ricky Chen wrote on Oct 31st, 2011, 11:58pm:
SWITCH CAP  CMFB circuit.
By the way the above circuits are the snapshot of one state of SWITCH CAP sense circuit


None of us can read minds.
You never said anything before about this.
Please define your probably correctly in the
future, and do not assume we have the capability
read your mind from the other side of the planet.

My mind reading capabilities are limited to under a 300km range.
:D


Hello Loose-Electron

After knowing that it is a switch-cap CMFB, do you have any answer to my question ? How DC f/b is NOT in the circuit ?

Sorry for trying to read people's mind.
Thanks for letting the forum know about your reading CAPABILITY

Title: Re: Common Mode Feedback Contorl
Post by Alexandar on Nov 2nd, 2011, 2:31am

Funny thread with all those cheesy smileys  :D.

Both structures have their advantages. The one without the DC bias can be advantageous if you want to spare on biasing circuits/routing. The one with DC will probably have better start up behavior, less leakage problems, better (large signal) common mode rejection and so on.

Title: Re: Common Mode Feedback Contorl
Post by Ricky Chen on Nov 2nd, 2011, 2:38am


Lex wrote on Nov 2nd, 2011, 2:31am:
Funny thread with all those cheesy smileys  :D.

Both structures have their advantages. The one without the DC bias can be advantageous if you want to spare on biasing circuits/routing. The one with DC will probably have better start up behavior, less leakage problems, better (large signal) common mode rejection and so on.


thanks a Lot !! Alexander

Can you please explain why it will have better (large signal) common mode rejection ?
You may point to any literature which actually explains this large signal CM behavior in CMFB circuit

Title: Re: Common Mode Feedback Contorl
Post by loose-electron on Nov 2nd, 2011, 6:49pm

The circuit that only control part of the common mode is preferred in my opinion.

With only partial amounts of the current under control, you will be less likely to create wide erratic behavior ion the common mode signal.

One circuit can fully turn the bias current on/pff, the other one can adjust things up-down in a smaller amount.

Title: Re: Common Mode Feedback Contorl
Post by RobG on Nov 3rd, 2011, 2:21pm

Maybe Ricky should change his chance his avatar to Wilma so I can tell him from loose e- (as in loose e, I'm home).

I don't know a ton about cap cmfb, but the circuits I've seen switch both sides of the cap to reference points during a reset cycle. This allows a voltage drop across the caps to the fb device and the CM output to be biased at any level desired. If resistors were used there would be no DC drop and the either the fb device or the diff pair would be linear except within a very small range of input common mode bias with this particular topology. (Although a dc current could be injected at node P to level shift the output common mode level.)

You'd like the FB device to supply only a small current to keep the common mode gain small, especially for increased stability (IE the parallel DC tail source supplies most of the current). The danger of this is that if mismatches cause the parallel DC tail current to be more than the PMOS currents the fb device will be completely off and the output will be pulled low.

Low CMFB gain also means the common mode output will deviate a larger amount from ideal since the FB device will need more gate drive to make up for mismatched tail/load currents.


addendum... I'm pretty sure this circuit is meant to be reset as opposed to using resistances. The resistances are not needed: one could use simply use two NMOS FB devices: both drains tied to the tail, and the first/second gates tied to the left/right outputs respectively.

Title: Re: Common Mode Feedback Contorl
Post by loose-electron on Nov 6th, 2011, 5:33am

Ricky:

You really need to ask the question in a better fashion.

If the circuit is a switched capacitor system, you need to show all states and switches.

Acquisition phase, zero out phase, control phase - whatever you got.

Thing is you can get a switched cap system to deal with CMFB and all that put you need to show whats going on in all phases and control points of your switching.

If the system is run switch cap and includes proper zero and precharge of all capacitors, it can work properly. For something like that, a fixed DC current on the bias is NOT wanted, because then it injects a leakage effect that causes the control voltages on the capacitors to discharge/droop.

Ask your question again with a better definition of the problem.

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