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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> exponential delay on/off transition? https://designers-guide.org/forum/YaBB.pl?num=1320766491 Message started by niikos on Nov 8th, 2011, 7:34am |
Title: exponential delay on/off transition? Post by niikos on Nov 8th, 2011, 7:34am Hi everyone, I would like to apply an exponential time delay to an current source that i model using verilog-a using Cadence. I would like something like the transition operator but with emponential delay not a linear. One more thing is that I want the on time delay to be different than the off time delay. I have tried to implement this using RC network, but the network messes up the function of the circuit in time slots it supposed not to. Any other idea? |
Title: Re: exponential delay on/off transition? Post by boe on Nov 11th, 2011, 8:25am Niikos, Try decoupling from the load. If you need more help, I suggest you post your code. - B O E |
Title: Re: exponential delay on/off transition? Post by niikos on Nov 12th, 2011, 4:15am this is what i did. thanks |
Title: Re: exponential delay on/off transition? Post by Marq Kole on Nov 13th, 2011, 1:03pm To get a proper time domain behavior that looks like a exponential rise/fall you need to make sure you get enough time points. The best way to achieve this is by using the $bound_step system task. If you use a linear rise from the transition operator as input and just map the linear value to the equivalent exponential value you should be able to calculate arguments to the $bound_step task that control the step size to be sufficiently small during transition while switching off this step size control when it has reached its final value. Cheers, Marq |
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