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Design Languages >> Verilog-AMS >> what is the purpose to use rega<=datain & dataout<=rega?
https://designers-guide.org/forum/YaBB.pl?num=1321000234

Message started by newic on Nov 11^th, 2011, 12:30am

Title: what is the purpose to use rega<=datain & dataout<=rega?
Post by newic on Nov 11^th, 2011, 12:30am

Code:

module test(
reset, clk, datain, dataout);

input [7:0] datain;
output [7:0] dataout;
input clk, reset;

reg [7:0] rega;
reg [7:0] dataout;

always @ (posedge clk or posedge reset) begin
if( reset ==1'b1) begin
rega <= 8'b0;
dataout <= 8'b0;
end
else begin
rega <=datain;
dataout <= rega;
end

endmodule

May I know what the purpose to use rega<=datain & dataout<=rega?
if datain is 1001 0011, what is the expected output?

Title: Re: what is the purpose to use rega<=datain & dataout<=rega?
Post by Marq Kole on Nov 13^th, 2011, 1:17pm

[smiley=huh.gif] You could just have written a test bench and run it if you wanted the answer...

It delays the output by one clock edge, so if the input is 1001 0011 at the first rising edge of clk/reset, the output will be xxxx xxxx. On the second rising edge of clk/reset it will be 1001 0011. That's because in the non-blocking assignments all right-hand sides that occur at the some simulation time point will be evaluated first and only after that the assignments will be done. As the first value of rega is its initial value, i.e. xxxx xxxx, that is what is assigned to dataout at the same time as 1001 0011 is assigned to rega.

Cheers,
Marq