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Design Languages >> Verilog-AMS >> Getting cadence convergence error for VerilogA code
https://designers-guide.org/forum/YaBB.pl?num=1321083422

Message started by yash59 on Nov 11^th, 2011, 11:37pm

Title: Getting cadence convergence error for VerilogA code
Post by yash59 on Nov 11^th, 2011, 11:37pm

Hi,

I want to write verilogA code for the symbol having three pins(cop,vdd,vss) all are inout pins.

Function: when vdd is greaterthan 3v and vss is 0, take input from cop and i have to send output from the same pin(cop).

I have written follwing code.

`include "constants.vams"
`include "disciplines.vams"

inout cop,vdd,vss;
voltage cop,vdd,vss;

real copin;

analog begin

copin=V(cop);
if(V(vdd>=3 && V(vss)==0)
begin
V(cop)<+ copin;
end
else
V(cop)<+0;
end
endmodule

with this code i am getting cadence convergence error.. plz help inthis regard.

thanks,

Title: Re: Getting cadence convergence error for VerilogA code
Post by Forum Administrator on Nov 12^th, 2011, 2:25am

Normally when you don't give the actual model, or the testbench, or the error message, you make it quite difficult to help you (it is like you think we are psychic). However in this case, you yourself point out the problem. You are measuring the voltage of a pin, and then setting the voltage of the same pin to that value. In otherwords, your model states that:

Code:

copin=V(cop);
V(cop)<+ copin;

This can be simplified to:

Code:

V(cop)<+ V(cop);

The problem is that any voltage will satisfy that equation. Thus you have created a system where the solution is not unique, and simulators will not solve such systems. That is not really a problem in this case because this model makes no sense. Perhaps you can describe what you are trying to model and we can make suggestions.

-Ken