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Design >> Analog Design >> PLL BW
https://designers-guide.org/forum/YaBB.pl?num=1321481076

Message started by summi on Nov 16^th, 2011, 2:04pm

Title: PLL BW
Post by summi on Nov 16^th, 2011, 2:04pm

dear forum,
can any please tell me is there any way to simulate PLL BW and damping factor through transient simulations? Because while designing i have some math and calculated loop filter parameters and Icp based on Kvco, but after design how to verify? At least in lab how people characterize PLL BW, becaue it is more imp for wireless PLLs.

Br,
Summi.

Title: Re: PLL BW
Post by raja.cedt on Nov 17^th, 2011, 1:29am

hello summi,
it is very difficult to simulate PLL dynamics with transient noise (at least i haven't done), but may be you can apply to N*fref and then change it to (1+N)*fref, so try to find some correlation from settling, but i am sure BW can be estimated by simulating PLL phase noise through transient noise, VCO Phase noise and then see from which point PLL phase noise follow's VCO noise.

But while mesurement BW can estimated by modulating the reference clock frequency and see till what frequency O/P is able to track, thats the BW.

Thanks,
raj.

Title: Re: PLL BW
Post by summi on Dec 22^nd, 2011, 4:23pm

dear raja.cedt,
thanks you so much for your reply, but i didn't understand BW measurement, could you please explain more.

Br,
Summi.

Title: Re: PLL BW
Post by raja.cedt on Dec 23^rd, 2011, 5:08am

hello,
PLL bw means, what is the max frequency of the reference-frequency at which o/p tracks. there are many ways to do it, here is the 2 method i know
1. modulate the refclk phase at various offset frequencies (e.g. 50kHz to 20MHz) and measure the height of the resulting spurs on the spectrum analyzer. I define the height of the spur at the lowest modulation frequency as the 0dB point on the closed-loop transfer function H(s) and then generate the rest of H(s) by subtracting the height of the other spurs from this base value. This yields accurate measurement of the bandwidth (-3dB) but sometimes does not allow us to accurately measure peaking for well-overdamped PLLs (e.g. peaking < 0.5dB). The problem with peaking is that it can be difficult to accurately determine the 0dB point to within a few tenths of a dB. Note that you want to enable averaging on the spectrum analyzer to lower its noise floor.

2. I apply a small phase step (say 1ns-5ns) to the reference clock of the PLL and capture the PLL output frequency vs. time on an oscilloscope as the PLL re-locks. Next, I do an FFT of this frequency vs. time data. The magnitude of the FFT at any given offset frequency relative to the FFT magnitude at the lowest offset frequency forms the PLL closed-loop transfer function. This "normalization" is similar to what we did with the spectrum analzyer.

Why does this method work? When we apply a phase step to the PLL, we're basically exciting it at all frequencies at the same time. Remember that the derivative of a phase step is a delta function, and the FFT of a delta function is white noise. So, to be consistent with the applied input, we need to do an FFT of the DERIVATIVE of the PLL phase response. That derivative is the PLL output frequency. To improve the SNR of the measurement, you need to average the results of say 64 separate phase steps. Note that if you apply too big an input step, the PLL response may become non-linear, and the resulting closed-loop transfer function will be inaccurate. Too small a step and your SNR goes down.

Thanks,
raj