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The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> question about charge pump in PLL https://designers-guide.org/forum/YaBB.pl?num=1321535035 Message started by lonemy on Nov 17th, 2011, 5:03am |
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Title: question about charge pump in PLL Post by lonemy on Nov 17th, 2011, 5:03am Dear All: I have a question about the stability of charge pump in PLL. the ckt is like attachment fig.1. if the charge pump sink current to the LPF, there two loops in ckt, like fig.2. we can see that loop1 is a negative feedback loop and loop2 is positive. my question is: at low frequency, the impedance of LPF is larger than ro2, so the positive feedback is stronger than negative feedback, then the ckt is not stable, but in real case, this ckt works normally, could anyone tell me where my mistake is ? thank you~ |
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Title: Re: question about charge pump in PLL Post by raja.cedt on Nov 17th, 2011, 5:37am hello, yes you are correct, you have to design in such a way that -ve loopgain > +ve feedback. I also doubt how to make -ve loop strong here but i wanted to tell you that due to higher impedance of the loopfilter +ve feedback wont be stronger because it is parallel with pmos transisters. But i have never seen this kind of CP!! Thanks, Raj. |
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Title: Re: question about charge pump in PLL Post by buddypoor on Nov 17th, 2011, 5:42am Lonemy, I don't think it is correct in this case to apply the small signal loop gain model. Rather, the circuit is designed as a switch to provide pulses. |
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Title: Re: question about charge pump in PLL Post by raja.cedt on Nov 17th, 2011, 5:51am hello buddypoor, you are correct, but i guess it is a bias ckt for charge pump (he has to seperate loopfilter from this ckt). I have a doubt here, forget about chargepump action,here how to make -ve feedback stronger? Thanks, raj. |
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Title: Re: question about charge pump in PLL Post by lonemy on Nov 17th, 2011, 10:30pm Dear Raja: attachment is the paper which introduce this kind of CP. |
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Title: Re: question about charge pump in PLL Post by lonemy on Nov 17th, 2011, 10:31pm buddypoor wrote on Nov 17th, 2011, 5:42am:
Dear Sir: as you told, how can I check the stability of this kind of ckt? thanks |
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Title: Re: question about charge pump in PLL Post by loose-electron on Nov 18th, 2011, 9:28am You may want to also take a look at classic H-bridge driver charge pumps as well. The shown device does not maintain the voltage points of the switches, (while both open and shut) which will lead to some problems as well. Fixed one problem and created another. |
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Title: Re: question about charge pump in PLL Post by lunren on Dec 4th, 2011, 2:53pm I think this charge pump is only stable above certain switching frequency. If you want to lower the stable frequency, maybe one way is to change the current mirror ratio. |
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Title: Re: question about charge pump in PLL Post by loose-electron on Dec 5th, 2011, 9:46am do you need the complexity here? generally a simple current mirror with ok geometry matching is sufficient. perfect up-down matching does not get you much other than a publication paper. |
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Title: Re: question about charge pump in PLL Post by RobG on Dec 5th, 2011, 12:22pm lonemy wrote on Nov 17th, 2011, 5:03am:
The loops do not look like they interact to me - just make sure that loop1 is stable to start with. Loop 2 is positive, but don't look at it's DC gain or small signal critera - pure positive feedback won't make an oscillator - it will just force the output to a rail. Don't worry about it -- the system should be designed around this circuit to prevent it from sticking at a rail. You need to look at the stability of the *system*. The stability of the system is determined by how long the switch is on and the time constant of the LPF - look at the voltage change at the LFP when the switch is turned on for "dT" seconds. It will change dV = Idc/C*dT. Yes, Idc has a small dependance on the current output (i.e. positive feedback additional current from ro2) but the contribution of ro2 will be small. Even if it is not, you are only worried about the amount of dV, not how you got it. You can do a discrete time analysis and check the stability of the *system* but it doesn't have much to do with the positive feedback in loop2. The instability you want to avoid is having the LPF jump rail to rail with each update. You prevent that by limiting the maximum charge time and/or making the cap large enough to prevent a large jump. I doubt you will have to worry about this as I'm positive that the settling requirements for the PLL itself will impose far more restrictive conditions to ensure stability. |
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Title: Re: question about charge pump in PLL Post by loose-electron on Dec 5th, 2011, 3:11pm Why even use the Op-amp for all the fancy bias? It will not match perfectly due to non ideal characteristics of the op-amp! Simple current mirrors, H bridge structure, it works well, and has been used many times |
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Title: Re: question about charge pump in PLL Post by RobG on Dec 5th, 2011, 4:27pm I think it would be an order of magnitude increase in signal dependent U/D matching even with opamp imperfections, but as you noted it may not improve the overall performance of the PLL loop. FWIW, the circuit in the paper is slighter different. rg |
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Title: Re: question about charge pump in PLL Post by lunren on Dec 5th, 2011, 6:29pm loose-electron wrote on Dec 5th, 2011, 3:11pm:
Hi Jerry, I am interested in this H bridge structure charge pump, can you give me a link or reference? Thanks, Lunren |
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Title: Re: question about charge pump in PLL Post by loose-electron on Dec 6th, 2011, 2:15am ece.wpi.edu/analog/resources/PLLTutorialISSCC2004.pdf see page 50 of the above |
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Title: Re: question about charge pump in PLL Post by lunren on Dec 6th, 2011, 4:56am Hi Jerry, Thanks a lot. |
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Title: Re: question about charge pump in PLL Post by RobG on Dec 6th, 2011, 6:50am loose-electron wrote on Dec 6th, 2011, 2:15am:
I like it 8-) |
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Title: Re: question about charge pump in PLL Post by loose-electron on Dec 6th, 2011, 10:12am I refine that structure a bit with: Minimum size transitors in the H bridge to minimize charge injection. PMOS transistors top of bridge only. NMOS transistors bottom of bridge only limit signal amplitude ti the 4 currrent steering switches All of the above gets the device closer to ideal switches to redirect the charge pump current and reduce transient signal current injection. |
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Title: Re: question about charge pump in PLL Post by lunren on Dec 13th, 2011, 10:50pm loose-electron wrote on Dec 6th, 2011, 10:12am:
Hi Jerry, Why you didn't use CMOS switches? I think based on the modifications you did (small size and limited signal swing to control switches), if you use CMOS instead only PMOS on top and only NMOS on bottom, it might be better to reduce charge sharing and clock feedthrough? By the way, with your modification, how much reference spur can you get with this charge pump? Thanks, Lunren |
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Title: Re: question about charge pump in PLL Post by RobG on Dec 16th, 2011, 11:18am lunren wrote on Dec 13th, 2011, 10:50pm:
Lunren, I think Jerry is talking about using diff-pairs to steer current instead of switches. With a diff pair you only need a few hundred millivolts to steer the current between the opamp output and the capacitor network. rg |
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Title: Re: question about charge pump in PLL Post by loose-electron on Dec 18th, 2011, 2:13pm At the end of the day it looks more like current steering than rail to rail gate driven switches. Spurs? Depends on your primary hold capacitors and similar issues. Specific numbers are unique to a system. Key thing here is getting the current steering switches to look as close to ideal as possible. Also, things like the PFD need to account for the zero phase point and avoiding deadbanding issues. PLL's have a lot of little things that affect performance. I could write a book! |
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Title: Re: question about charge pump in PLL Post by lunren on Dec 18th, 2011, 11:30pm Hi Rg, I got it. Thanks. |
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Title: Re: question about charge pump in PLL Post by lunren on Dec 18th, 2011, 11:53pm loose-electron wrote on Dec 18th, 2011, 2:13pm:
Hi Jerry, What do you mean by zero phase point? I think you are saying the phase difference between reference clock and feedback clock should be zero, right? But I think this phase error is more related to mismatching in charge pump other than PFD itself (assuming the up and down path in PFD is perfectly matching). |
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Title: Re: question about charge pump in PLL Post by loose-electron on Dec 19th, 2011, 12:18pm Zero phase point is when the two inputs to the PFD are exactly in line with each other. Behavior needs to be carefully examined here. PFD at this point is often created to give equal size up-down pulses Static phase errors are what you mention, offsets, mismatches, etc. |
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Title: Re: question about charge pump in PLL Post by aaron_do on Dec 19th, 2011, 5:40pm Quote:
Looking forward to it :D |
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Title: Re: question about charge pump in PLL Post by Lex on Dec 19th, 2011, 11:39pm loose-electron wrote on Dec 18th, 2011, 2:13pm:
Do you already accept pre-orders? ;D |
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Title: Re: question about charge pump in PLL Post by loose-electron on Dec 21st, 2011, 10:43am Thing is electronics books don't sell to a wide audience. It's on my bucket list.... Serious interest? |
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Title: Re: question about charge pump in PLL Post by Forum Administrator on Dec 21st, 2011, 11:48am Jerry, Writing a book is a big endeavor, and if it does not become a widely used textbook is generally not that profitable. As an alternative, you might consider writing smaller tutorials. I would be happy to publish them on this site. You would not make any money of course, but you can have a big impact. -Ken |
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Title: Re: question about charge pump in PLL Post by aaron_do on Dec 21st, 2011, 4:30pm Throughout my postgrad studies - and even now - I've been looking for that book that will explain things in a more engineering fashion. i.e the practical implementation of all the fundamentals we see in textbooks and papers. I think it would be a good read and a useful reference...I'm always looking for good tutorial papers too though. Aaron |
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Title: Re: question about charge pump in PLL Post by loose-electron on Dec 22nd, 2011, 4:14am Forum Administrator wrote on Dec 21st, 2011, 11:48am:
Ken: Yeah, I am very aware that its a thankless and profitless endeavor. McGraw Hill wanted me to do something for them a while back and I deferred due to lack of time and sufficient financial motivation. Let me give some thought to your suggestion. Jerry |
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Title: Re: question about charge pump in PLL Post by loose-electron on Dec 22nd, 2011, 4:20am aaron_do wrote on Dec 21st, 2011, 4:30pm:
Well, as a reviewer for 6-8 years for both IEEE JSSC and IEEE MTT, I was always pushing for the inclusion of the practical and useful aspects in addition to the mathmatical analysis. Never happened, you review a paper with a panel of others and it gets shot down. Most reviewers are coming at it from the view of a university professor. Thats the big reason I write for the trade magazines instead. |
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Title: Re: question about charge pump in PLL Post by Lex on Dec 23rd, 2011, 12:24am loose-electron wrote on Dec 6th, 2011, 2:15am:
Great piece. I especially like the “Spectacular” Failures and Design for test. |
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Title: Re: question about charge pump in PLL Post by loose-electron on Dec 23rd, 2011, 5:00pm welcome to the real world... :) |
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Title: Re: question about charge pump in PLL Post by raja.cedt on Jan 25th, 2012, 8:08am hello all, is any one got conclusion for this post, i mean he Question is how here +ve feedback behave here? What i feel is +ve FB has less loop gain, because loop filter control node will be low impedance. Thanks, Raj. |
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