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Design Languages >> Verilog-AMS >> assign vs wire command
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Message started by newic on Nov 18^th, 2011, 1:15am

Title: assign vs wire command
Post by newic on Nov 18^th, 2011, 1:15am

is there a different to use "assign" command and "wire" command for feedthrough signals??

output out, out_wire;
input in, in_wire

wire out_wire = in_wire;
vs
assign out = in;

any comment?
will the synthesis tool put buffer in between input & output ports?