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Design Languages >> Verilog-AMS >> Pulse generator in verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1321839981

Message started by ssp on Nov 20^th, 2011, 5:46pm

Title: Pulse generator in verilog-A
Post by ssp on Nov 20^th, 2011, 5:46pm

Hi,

I'm new to verilog-A and I'm trying to generate an output pulse of 0V at every falling edge of my input pulse signal (1.8V to 0V) in Spectre. Unfortunetly, using the following code, my output pulse seems to be generated at a rising edge :

Code:

`include "constants.vams"
`include "disciplines.vams"

module allo(in,out);
parameter real td = 3n; // width of pulse
parameter real tt = 0n; // output transition time (s)

output out;
input in;
voltage in, out;

real Vout, tend;

analog begin
@(cross(V(in), -1)) begin
Vout = 0;
tend = $abstime + td;
end
@(timer(tend))
Vout = 1.8;
V(out) <+ transition(Vout, td, tt);
end

endmodule

My resulting signals :

Title: Re: Pulse generator in verilog-A
Post by ssp on Nov 20^th, 2011, 9:02pm

To be more clear, this is the signal train I want to have :

[img][/img]

How can I obtain that output ?
Thank you for your help,
ssp

Title: Re: Pulse generator in verilog-A
Post by Forum Administrator on Nov 20^th, 2011, 11:24pm

Your model looks okay to me. Perhaps the problem is elsewhere. Please provide enough information so we can replicate your simulation.

-Ken

Title: Re: Pulse generator in verilog-A
Post by ssp on Nov 21^st, 2011, 7:15am

Hi Ken,

the problem is that my code doesn't generate the output pulse as I wich it did. It seems that the @cross function is not working well, or perhaps the code I made have a mistake in it that I can't detect...I don't know if this can help but my input signal comes from a dynamic comparator working with an intern clock of 12ns period. I want to use the output pulse as a reset signal for a PMOS transistor.

Title: Re: Pulse generator in verilog-A
Post by ssp on Nov 21^st, 2011, 7:18am

Also, my simulation was made using Spectre Cadence with a transient analysis.

Title: Re: Pulse generator in verilog-A
Post by boe on Nov 21^st, 2011, 7:37am

Hi,

Your cross event tests for negative crossing with threshold 0. This is probably not what you intended.

- B O E

Title: Re: Pulse generator in verilog-A
Post by ssp on Nov 21^st, 2011, 7:48am

Hi Boe,

yes, your right, that's the problem. Is there a way I can set the threshold voltage to 1.6V in the @cross function ? If not, is there a simple code to detect falling edge of a signal with min. 0V and max. 1.8V ?
Thanks!

Title: Re: Pulse generator in verilog-A
Post by ssp on Nov 21^st, 2011, 9:24am

By reading verilog-ams guide more carefully, I only need to add V(in)-1 in the cross function to make it work:

@(cross(V(in)-1,-1))

Title: Re: Pulse generator in verilog-A
Post by Geoffrey_Coram on Nov 22^nd, 2011, 10:38am

ssp wrote on Nov 21^st, 2011, 9:24am:

By reading verilog-ams guide more carefully

Always a good idea!

Title: Re: Pulse generator in verilog-A
Post by ssp on Nov 23^rd, 2011, 3:06pm

Hi guys,

I still don't exactly get the result I'm expecting with this code:

Code:

module allo(in,out);
parameter real td = 10n; // width of pulse
parameter real tt = 0n; // output transition time (s)
parameter real t1 = 0n;

output out;
input in;
voltage in, out;

real Vout, tend,rst;

analog begin

@ (initial_step or cross(V(in)-1, -1)) begin
// @ (cross(V(in)-1, -1)) begin
Vout = 0;
tend = $abstime + td;//return simulation time + td
end

@(timer(tend))
Vout = 1.8;
V(out) <+ transition(Vout, td, tt);
end

endmodule

I want to detect the first falling edge on the Vin signal (time 65.24ns), while my code only detects the second falling edge at time 75.21 ns. Why is that ? Is there a way I can fix my code to detect the first falling edge ?

Thanks for your help,
ssp

Title: Re: Pulse generator in verilog-A
Post by Forum Administrator on Nov 24^th, 2011, 1:07am

Never put a contribution statement or a transition function inside an @ block.

-Ken

Title: Re: Pulse generator in verilog-A
Post by boe on Nov 24^th, 2011, 4:42am

ssp wrote on Nov 23^rd, 2011, 3:06pm:

...
I want to detect the first falling edge on the Vin signal (time 65.24ns), while my code only detects the second falling edge at time 75.21 ns. Why is that ? Is there a way I can fix my code to detect the first falling edge ?

You do detect the edge @ 65.24 ns; because of the 10 ns delay you specified (td in transition filter), the output changes @ 75.24.

BTW, Ken: The contribution statement is not inside the @ block, the code is just poorly indented.

- B O E

Title: Re: Pulse generator in verilog-A
Post by ssp on Nov 24^th, 2011, 7:25am

wow, yes, I guess I was I tired when I wrote that..I add 2 delays with the transition.
I was wondering, at what rate does the @cross function samples signals ?

Title: Re: Pulse generator in verilog-A
Post by Forum Administrator on Nov 24^th, 2011, 1:24pm

Argh. Normally I will not answer questions from people that cannot be bothered to format their code in a readable fashion. I should have stuck with that policy here.

Code:

module allo(in,out);
parameter real td = 10n; // width of pulse
parameter real tt = 0n; // output transition time (s)
parameter real t1 = 0n;
output out;
input in;
voltage in, out;
real Vout, tend,rst;

analog begin
@(initial_step or cross(V(in)-1, -1)) begin
Vout = 0;
tend = $abstime + td;//return simulation time + td
end

@(timer(tend))
Vout = 1.8;

V(out) <+ transition(Vout, td, tt);
end
endmodule

Improperly indented code is largely unreadable, leading to confusion and mistakes, and making it hard for people to help you. Before asking someone to look at your code, you should indent it properly. It only took me a few seconds to do it, and in doing it you often find the problem yourself.

-Ken

Title: Re: Pulse generator in verilog-A
Post by boe on Nov 25^th, 2011, 4:56am

ssp wrote on Nov 24^th, 2011, 7:25am:

...
I was wondering, at what rate does the @cross function samples signals ?

See documentation: Cadence Verilog-A language reference, section cross-Event.

- B O E