The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Simulators >> RF Simulators >> Hidden States in SpectreRF & other simulators https://designers-guide.org/forum/YaBB.pl?num=1322228712 Message started by weber8722 on Nov 25th, 2011, 5:45am |
Title: Hidden States in SpectreRF & other simulators Post by weber8722 on Nov 25th, 2011, 5:45am Hi, SpectreRF has well-known problems with veriloga models if they have so-called hidden states. What about other RF simulators, do they have the same problem with veriloga? In principle there could be some clever internal algorithms to get automatically rid off hidden variables, e.g. by allowing access to them. I wonder if the Accellera group considers treating this problem? Bye Stephan |
Title: Re: Hidden States in SpectreRF & other simulators Post by sheldon on Nov 26th, 2011, 6:16pm Stephan, My feeling is that this is more of a perception issue than an actual issue. For example, once a customer gave me an ADC testcase written in Verilog-A. A simple ADC was taking several days to complete, if it did not fail to converge. A quick look at the models found the issue. The primitive components were all modeled with if, then, else statements. For functional simulations, this modeling style was fine. However, the primitives were being used as analog components in this particular simulation. So the primitive models needed to be re-written to have well-behaved analog behavior. Re-writing the models, the simulation finished in about 20m. So my thought is that is not so much of an unsolvable technical issue as the need to create a behavioral model optimized for an application. Modelers already create multiple model levels to address different simulation requirements: level0, level1, etc., so this does not seem to be that radical of a suggestion. The modeling style for periodic steady-state analysis is well known and documented. There is an S/H code sample in the switched capacitor white paper and the D-flip flop example. Another approach that can be useful is to reduce a block to its components. This works for example when trying to simulate the R/S flip-flop in a DC-to-DC Converter. While using the same models for transient analysis and PSS analysis would be convenient, even for, transient analysis the modeling style needs to be suited to the application. Best Regards, Sheldon |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |