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Design >> Analog Design >> How to decide offset frequency in phase noise?
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Message started by ana_dig_mixed on Nov 25^th, 2011, 5:54pm

Title: How to decide offset frequency in phase noise?
Post by ana_dig_mixed on Nov 25^th, 2011, 5:54pm

Hi,
I have relaxation oscillator(ROSC) as reference clock for PLL. Based on PSS/Pnoise simulation of ROSC, I have ~3ns of RMS jitter if I integrate phase noise from 1KHz to 1MHz of offset frequency. Most of them are contributed by below 100KHz of offset frequency and PLL does not care of this phase noise because its bandwidth is larger than 100KHz. This clock will be used for ADC sampling through PLL.

Now, here are my questions.

1) For communication system application, we will have offset frequency for phase noise in system specification. But for microprocessor, memory, or ADC clock, how do I decide offset frequency range to integrate phase noise to calculate jitter? Should I integrate phase noise from low offset frequency(~1KHz) to ADC sampling frequency? If so, what is criteria to select it?

2) I want to add phase noise in ROSC to phase noise of PLL. I did PSS/Pnoise simulation for ROSC only and apply the data of phase noise of ROSC to close loop transfer function of PLL in Matlab. I know this is one of reasonable ways to see phase noise of reference clock in PLL loop. But, phase noise from simulation(PSS/Pnoise) has a unit of dBc/Hz and meaning is that x-axis of phase noise starts just offset frequency from oscillation frequency(not 0,or dc), but PLL transfer function has different unit(dB), meaning is that response of this function does not start from oscillation frequency. For example, oscillation frequency is 8MHz, PLL BW=1MHz. If we put phase noise of ROSC and PLL transfer function on same plot, reference signal including phase noise will be filtered out by PLL. Is this right simulation to see how does phase noise of reference clock(ROSC) with PLL loop affect to total jitter?

I am looking for your helps.

Title: Re: How to decide offset frequency in phase noise?
Post by raja.cedt on Dec 2^nd, 2011, 2:13am

hello,
many times upper limit will be fc/2, but lower limits depends strongly on system design, for example in serial communication lower limit depends on CDR BW (which i smany times fc/1667). Like this for data converters also lower limit depends on several factor which was explained in detail here

http://www.ti.com/lit/an/slyt379/slyt379.pdf

I am also having so many doubts, so let us w8 for some expert will give the reply.

Thanks,
Raj.

Title: Re: How to decide offset frequency in phase noise?
Post by raja.cedt on Dec 2^nd, 2011, 8:34am

hello ana_dig_mixed,
PLL TF from input to output also with respect to offset frequency, because pll will respond to the frequency of the input frequency. Let us say you have Reference frequency is 100Meg, loop BW is 1Meg so X-axis in TF is frequency of frequency (means if input frequency is changing with f, then x axis would be like 100+f).

Thanks,
Raj.