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Design >> Mixed-Signal Design >> DRAM DESIGN
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Message started by chandu28 on Nov 29^th, 2011, 1:28am

Title: DRAM DESIGN
Post by chandu28 on Nov 29^th, 2011, 1:28am

Hello guys,
Iam M.S.Chandra Sekhar currently working(mtech-project) in the field of memory design and it is called "Design of 4Kb DDR SDRAM". I am simulating this in Design Architect (Mentor Graphics).For this project I started with DRAM design and I am stuck with it. could anyone please help me out. Actually the problem is with where to connect the refresh circuit. The order is like this (as I have used)sense amplifier,isolation circuit,cell,refresh circuit,write driver circuit. and I have connected the refresh circuit like a loop to the bitline and by using the pattern Iam running the circuit. The output Iam getting is both distorted and leveled up.
awaiting your reply.... :) :) :)

Title: Re: DRAM DESIGN
Post by loose-electron on Nov 29^th, 2011, 3:56pm

show a schematic please?

Title: Re: DRAM DESIGN
Post by chandu28 on Nov 29^th, 2011, 8:03pm

this is the schematic with complete blocks...can you tell me if all the connections were made correct or not....
thank you :) :)

Title: Re: DRAM DESIGN
Post by loose-electron on Nov 30^th, 2011, 11:19am

Oh, perfectly connected!
:(
Very difficult to tell whats what and all that.

Suggest you work on better formulation of the question here, can not really tell what you are doing from that drawing.

Title: Re: DRAM DESIGN
Post by AnalogDE on Nov 30^th, 2011, 4:11pm

Start with a bit-slice and get that working and understood. After that, then you can figure out how to draw the array schematics.

Title: Re: DRAM DESIGN
Post by chandu28 on Nov 30^th, 2011, 9:17pm

actually this is the schematic of a 1 row DRAM design each block is working individually starting from the top sense amplifier,isolation circuit , cells(row of cells) write driver circuit refresh circuit and at he end column decoder...
we know that the main problem in any design is the connections to various blocks i dunno where the mistake is... thats what is my question sir...

Title: Re: DRAM DESIGN
Post by raja.cedt on Dec 1^st, 2011, 12:04pm

hello chandu,
is your refresh ckt working fine, means is it able to write what it have read from the cell in the given time? refer wste and harris digital design he has pointed out many common mistakes...

Thanks,
Raj.

Title: Re: DRAM DESIGN
Post by loose-electron on Dec 1^st, 2011, 2:23pm

chandu28 wrote on Nov 30^th, 2011, 9:17pm:

OK, then suggest you start by using the blocks to build and simulate as you build parts of the schematic until the response is not as expected.

Divide the problem and understand it as you go.

Also, if you think there is an unexpected loading effect someplace you may want to either monitor currents in connections, or insert ideal voltage to voltage buffers in lines to determine where the loading problem is.

Title: Re: DRAM DESIGN
Post by chandu28 on Dec 1^st, 2011, 7:19pm

raja.cedt wrote on Dec 1^st, 2011, 12:04pm:

hello Raj,
Yes it is I just gave a random pulse with 1v p-p and vdd to the refresh circuit as 5 v p-p with pattern and I got the result exactly as I expected...

Title: Re: DRAM DESIGN
Post by chandu28 on Dec 1^st, 2011, 7:25pm

loose-electron wrote on Dec 1^st, 2011, 2:23pm:

sure sir i get to it right away and since Iam connecting the bit and bitbar lines so close will there be any capacitance effect??? and also can we check sense amplifier individually? because Iam not getting proper swing too.... :) :)

Title: Re: DRAM DESIGN
Post by loose-electron on Dec 2^nd, 2011, 12:06pm

If all the individual peieces work as expected -
Isolate the parts using voltage to voltage buffers.

That will teach you if its a loading issue.

Title: Re: DRAM DESIGN
Post by chandu28 on Dec 2^nd, 2011, 10:20pm

loose-electron wrote on Dec 2^nd, 2011, 12:06pm:

If all the individual peieces work as expected -
Isolate the parts using voltage to voltage buffers.

That will teach you if its a loading issue.

Sir,
Can you please be more elaborate???

Title: Re: DRAM DESIGN
Post by loose-electron on Dec 3^rd, 2011, 7:34pm

you have the design of several different pieces in your system.

all of them should have been simulated and designed to work as expected

after that, you have connected them together and something is broken.

Correct so far?

If you use a "voltage to voltage" converter in SPICE/Spectre with G=1 on any and all of the connections between boxes, you should be able to get
the boxes functioning again because now the boxes no longer interact or load each other down.

Title: Re: DRAM DESIGN
Post by chandu28 on Dec 3^rd, 2011, 7:48pm

yes sir you are right...by then I can find the fault location....I will try it sir...

Title: Re: DRAM DESIGN
Post by loose-electron on Dec 4^th, 2011, 12:31pm

not a problem, happy to help,
Jerry

Title: Re: DRAM DESIGN
Post by chandu28 on Dec 6^th, 2011, 10:46pm

I found out the error sir ... its the decoder which I have used... its giving 2v output when I give 11 as input and nearly 1 for other 3 inputs.... can you suggest me some which can give equal outputs??? :) :) :)

and also the swing is too low please see the pictures

Title: Re: DRAM DESIGN
Post by chandu28 on Dec 6^th, 2011, 10:46pm

this is another example... can you please suggest some methods????

Title: Re: DRAM DESIGN
Post by loose-electron on Dec 7^th, 2011, 9:42am

Is the fault in the circuit, or due to the load on the circuiit. (see prior suggestion on buffers to isolate)

start there.

Title: Re: DRAM DESIGN
Post by chandu28 on Dec 9^th, 2011, 3:26am

sir I have used a 2 inverter connected back to back kind of sense amplifier which is somehow acting as an inverter.... any suggestions????

Title: Re: DRAM DESIGN
Post by loose-electron on Dec 9^th, 2011, 5:50pm

The output of the inverter is probably attenuating the signal, the two devices ar both trying to pull the node in different directions. The result is attenuation or voltage division depending on the size of the transistor involved.

Title: Re: DRAM DESIGN
Post by chandu28 on Dec 9^th, 2011, 8:49pm

so how can I reduce it sir??? its effect is more than loading effect.... do I have to vary the transistor sizes???

Title: Re: DRAM DESIGN
Post by loose-electron on Dec 10^th, 2011, 10:15am

Which device do you want to provide the most signal?

That one should use bigger W/L transistors.

Usually 2 inverter latch structures have small W/L devices so another device with bigger W/L transistors can flip the latch back and forth.

Title: Re: DRAM DESIGN
Post by chandu28 on Dec 10^th, 2011, 8:39pm

sir I am generally considering PMOS as a base...

I think since I am not using the output of the bitline bar only one side of the latch is being used and hence it is acting as an inverter... am I correct sir???
If so how can I proceed further sir???

Title: Re: DRAM DESIGN
Post by loose-electron on Dec 12^th, 2011, 12:19pm

Back to back inverters will act like an SR latch, if you
drive the device properly.

It is a memory device with the driver removed.

When one side or the other is forced high-low the inverters function as inverters.

Title: Re: DRAM DESIGN
Post by chandu28 on Dec 27^th, 2011, 5:31am

yes sir it does..
I have another doubt sir .... now how can I convert it to sdram....we know we can do this by adding clock to the system... my question is how exactly.... can you please through some light on it.
awaiting your reply..
sincerely,
M.S.Chandra Sekhar :)

Title: Re: DRAM DESIGN
Post by loose-electron on Dec 27^th, 2011, 1:09pm

You really need to do some research and reading on this subject.

http://technav.ieee.org/tag/8571/sdram
http://en.wikipedia.org/wiki/Static_random-access_memory
http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/4/4317684/04317699.pdf?arnumber=4317699

Start there. Also search for vendors who
make SDRAM chips and read their documentation.

Title: Re: DRAM DESIGN
Post by chandu28 on Jan 6^th, 2012, 1:13am

thank you sir....

sir,can I redraw sense amplifier as shown in the picture.....theoretically it should work well but practically it isn't can you through some light here.

sincerely,
M.S.Chandra Sekhar

Title: Re: DRAM DESIGN
Post by loose-electron on Jan 6^th, 2012, 1:41pm

The sense amplifier that you have may not have the needed gain, it is a single logic inverter.

More gain, and a way of matching the center null point
(average of Vmax, Vmin) of the holding cell to gin amplifier are needed.

Maybe 3 inverters in series would be sufficient, perhaps a comparator
amplifier structure could be considered.

Title: Re: DRAM DESIGN
Post by raja.cedt on Jan 6^th, 2012, 2:12pm

hello loose-electron,
i guess you need gain otherwise it takes more time regenerate.

Thanks,
Raj.

Title: Re: DRAM DESIGN
Post by loose-electron on Jan 8^th, 2012, 1:30pm

raja.cedt wrote on Jan 6^th, 2012, 2:12pm:

hello loose-electron,
i guess you need gain otherwise it takes more time regenerate.

Thanks,
Raj.

Not sure what the OP is looking for here.
Help when you can right?

Title: Re: DRAM DESIGN
Post by chandu28 on Jan 9^th, 2012, 9:26pm

thank you sir for the links they very informative.....:)
now the question is how to get the hardware form...
from the information i gathered, i can draw an FSM or write a code in C or Verilog...but how to get it to hardware form....means circuit diagram sir....
Sincerely,
M.S.Chandra Sekhar.

Title: Re: DRAM DESIGN
Post by chandu28 on Jan 27^th, 2012, 9:01am

hello sir,
i have an idea like writing a code for sdram controller,after that synthesizing the code which gives me a schematic...
i will redesign the schematic and connect it to the main diagram....

will that work??? :) :-/
awaiting your reply...
sincerely M.SChandra Sekhar

Title: Re: DRAM DESIGN
Post by chandu28 on Feb 2^nd, 2012, 8:33pm

Hello sir
I have simulated a code in Xilinx ISE and synthesized it too. after that I got two schematics RTL and technology .... If I want to use the schematic for another circuit in mentor graphics which one to use????
awaiting your reply,

sincerely ,
M.S.Chandra Sekhar

Title: Re: DRAM DESIGN
Post by loose-electron on Feb 11^th, 2012, 5:22pm

It is very difficult to answer questions on things that should be found by your efforts in textbooks, published papers, applications notes and guidelines to using design tools.

Reads the manuals on the design tools, search the internet for information on transporting designs between design tools. If you have a target design platform you are going to make something on, ask the supporters of that platform how to use it and how to transport designs into it.

All of these things are part of being a design engineer.

Title: Re: DRAM DESIGN
Post by chandu28 on Feb 11^th, 2012, 7:47pm

Thank you sir :) :)

sincerely
M.S.Chandra Sekhar