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Design Languages >> Verilog-AMS >> how to monitor analog signal using verilog-ams
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Message started by xuedashun on Dec 2^nd, 2011, 8:22am

Title: how to monitor analog signal using verilog-ams
Post by xuedashun on Dec 2^nd, 2011, 8:22am

If I have 3 analog blocks: AAA BBB CCC, AAA is toplevel block, BBB is inside AAA and CCC is inside BBB block, if these is an analog signal called as xxx in CCC, now I want to monitor the xxx signal in another block (verilogams), how to do this in verilogasm?

I know if they are digital, we can use assignment to do it
wire xxx_monitor = AAA.BBB.CCC.xxx;

I read the Ken Kundert's book: The Designer's Guide to Verilog-AMS, but did not find which command or function I can use in verilogams.

Could you give me some suggestions? Thank you!

Title: Re: how to monitor analog signal using verilog-ams
Post by Geoffrey_Coram on Dec 5^th, 2011, 1:13pm

I would expect you could do
real xxx_monitor;

xxx_monitor = V(AAA.BBB.CCC.xxx);

but you'll have to write some kind of function to decide if the value has changed "enough" to warrant printing. A digital $monitor isn't appropriate for an analog value, which will change by tiny amounts (every iteration of) every timestep.

Title: Re: how to monitor analog signal using verilog-ams
Post by Marq Kole on Jan 17^th, 2012, 5:41am

Use the absdelay event function if you're using Cadence tooling (it is a Cadence propietary extension).

Code:

real xxx_monitor;

always
@(absdelay(V(AAA.BBB.CCC.xxx), 10m))
xxx_monitor = V(AAA.BBB.CCC.xxx);

For non-Cadence tooling you can do the same but using the above event function:

Code:

real xxx_monitor;

always
@(above(abs(V(AAA.BBB.CCC.xxx) - xxx_monitor) - 10m))
xxx_monitor = V(AAA.BBB.CCC.xxx);

Cheers,
Marq