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Design >> Analog Design >> 4-quad current multiplier
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Message started by muffassir on Dec 7^th, 2011, 3:39am

Title: 4-quad current multiplier
Post by muffassir on Dec 7^th, 2011, 3:39am

hi all,

Here is below my attached schematic of the 4-quad multiplier using translinear principle in subthreshold operation.

The above two oval marked are the Iin1=3nA , Iin2=3nA ,Vdd=0.4V , Ibias in the left of fig is Ibias=3nA , Vbias (below the FGMOS transistors) has the value Vbias=0.4V . input capacitors in the FGMOS are 150fF each at the input terminals (gate) of the PMOS .All MOS are of the same size.

I am doing the DC analysis(parametric) of the above circuit. for Iin1=-3nA to 3nA. And Iin2=-3nA to 3nA with 1nA steps. I expect to get the waveform(ignore the values of Iin1 and 2 in this image) as below.

But i am getting constant 3nA for all values of Iin3 .

Please correct my circuit where its going wrong and suggest me the answer.

Thanks .

Title: Re: 4-quad current multiplier
Post by loose-electron on Dec 7^th, 2011, 9:16am

3nA ??? What are the error tolerance settings on your simulator?

Title: Re: 4-quad current multiplier
Post by Vladislav D on Dec 7^th, 2011, 10:04am

Are you sure that sources of all transistors are connected to ground? In this case, you don't have more than 2 transistors in any translinear loop in the circuit...It's not gonna work as a multiplier.

Title: Re: 4-quad current multiplier
Post by muffassir on Dec 7^th, 2011, 7:35pm

loose-electron wrote on Dec 7^th, 2011, 9:16am:

3nA ??? What are the error tolerance settings on your simulator?

Yes sir,, I am using low vdc voltage to bias the transistors in the subthreshold region .so i am using 3nA current..further i am using Cadence virtuoso ADE L simulator using 180nm gpdk library from cadence.

I am newbie to both cadence AND analog design .I request you to give me the answers in detail that where the design is not correct .wht i should change to get the desired multiplier output.

Thnks in advance!!

Title: Re: 4-quad current multiplier
Post by muffassir on Dec 7^th, 2011, 8:00pm

Vladislav D wrote on Dec 7^th, 2011, 10:04am:

Hi Vladislav Sir,

Thanks for your reply,

Ya i have checked the ckt and all the nmos (middle line of 7 nmos FGMOS transistors)sources are connected to the ground and pmos(upper line of transistors) sources are connected to the vdd.

Upper transistors acts as current mirrors, middle line act as for multiplication and the lower two pmos acts as again current mirrors.

Further middle transistors count from left M1 ,M2 ....M7.

Here M2,M4,M5,M6 are the core elements, and M1,M3, M7 duplicate the currents of M2.M4 M6 respectively forming translinear loop.
IMi is the current tru Mi transistor where i=1 to 7
IM2 = IM1= Ib
IM4 = IM3 = Iin1+Ib
IM5 = (IM4 X IM6)/IM2 = (Iin 1 + Ib)(Iin2 + Ib)/Ib

IM6 = IM7 = Iin2 + Ib

If Iin1,Iin2 , Ib then outputs are

Iout1=IM1 + IM5
Iout2= IM3 +IM7

I hope i clarified my question now..

Hope now u r in better position to correct my ckt where its going wrong.

Thanks in advance.

Title: Re: 4-quad current multiplier
Post by loose-electron on Dec 8^th, 2011, 8:09am

You are trying to operate this circuit with small currents, possibly too small for simulator errors, or the definition of transistor model as defined by the foundry

Where are you on the bias curves for the transistors?

Title: Re: 4-quad current multiplier
Post by RobG on Dec 8^th, 2011, 11:56pm

I can't make sense of the circuit. Why do the NMOS devices in the translinear portion have two gates? and are you sure they are hooked up properly?

Title: Re: 4-quad current multiplier
Post by muffassir on Dec 9^th, 2011, 1:00am

RobG wrote on Dec 8^th, 2011, 11:56pm:

I can't make sense of the circuit. Why do the NMOS devices in the translinear portion have two gates? and are you sure they are hooked up properly?

Sir,

I am using the Floating Gate MOS for two inputs..This is for the use of further designing the neuron wherein there i can manipulate the weights by adjusting the values of input capacitors present at he gate of the floating gate..
& yes i am sure that they are hooked up correctly..Since this is the circuit from one of the IEEE paper which i am going to implement and also i have cross checked after your suggestion with the concepts of FGMOS.

Title: Re: 4-quad current multiplier
Post by muffassir on Dec 9^th, 2011, 1:12am

loose-electron wrote on Dec 8^th, 2011, 8:09am:

Dear Loose-electron Sir/Lady,

In gpdk180 the Vth=0.45V (approx) so,according to you what cuurents i should use..
For subthreshold Vds>4Vth,Vb=0...But i dont have idea about the currents...So please suggest me what currents i should use for my circuit so as to work?

Any if you have any idea about how to know the error tolerance setting of the simulator; you are welcome.
I am using CADENCE 6.1.4.500 and virtuoso,ADE L/XL. for the spectre simulations.
Thanks a lot ,

Muffassir

Title: Re: 4-quad current multiplier
Post by RobG on Dec 9^th, 2011, 1:31am

Muffassir - I think the best thing would be for you to show the dc currents of all the transistors for two different input currents. The answer will probably be obvious after you do this. If you repost it here please redraw the schematic so it is easier to understand.

best regards,
Rob

Title: Re: 4-quad current multiplier
Post by loose-electron on Dec 9^th, 2011, 9:53am

Jerry or Loos-electrons is fine...

:)

Plot a set of bais curves for your transistors, and show us for the voltages and currents where you are on those bias curves.

See:
http://www.electronics-tutorials.ws/transistor/tran11.gif

Title: Re: 4-quad current multiplier
Post by RobG on Dec 9^th, 2011, 11:33am

Jerry - I think if it were a tolerance or leakage issue there would still be *some* variation in the curve shown. Instead it is perfectly flat. Obviously none of the input signal is getting to the output side of the circuit. That is, it must be a connection error.

If he'd display the DC operating point showing Ids and Vds for two DC inputs it would be obvious where the problem it, even if it is a modeling/tolerance issue.

The circuit as drawn reminds me of what we used to call spaghetti code in computer programming. If a guy came in with it I'd refuse to debug it. Show the input and the output and add comments describing what the current in each leg should be! Just the act of organizing it usually solved the problem.

Title: Re: 4-quad current multiplier
Post by RobG on Dec 9^th, 2011, 11:49am

Vladislav D wrote on Dec 7^th, 2011, 10:04am:

OK, I lied and looked at the spaghetti circuit anyway.

Vladislav is absolutely right in my opinion. All of the NMOS transistor sources are connected to VSS so it is nothing more than a current mirror at best. I say at best because a proper current mirror output should have some dependance on its input, but without a proper definition of what those two gates are who knows what the circuit actually is. (How can you have a connection to a "floating gate anyway?).

A translinear loop needs to have a loop where Vgs1+Vgs2 = Vgs3 + Vgs4, which you do by connecting the source of two devices to the gates of two other devices. Then the gates of the top-most devices are also connected together creating a 4 transistor loop. https://www.google.com/search?q=translinear+circuit&oe=utf-8&rls=org.mozilla:en-US:official&client=firefox-a&um=1&ie=UTF-8&hl=en&tbm=isch&source=og&sa=N&tab=wi&ei=R2fiTsK5A6eWiALtz5muDw&biw=1355&bih=1103&sei=SWfiTrixEamviQKN8e2UAQ
This circuit has no such loop so it is nothing more than a current mirror.

Title: Re: 4-quad current multiplier
Post by RobG on Dec 9^th, 2011, 11:54am

sorry... double post which I can't seem to delete

Title: Re: 4-quad current multiplier
Post by RobG on Dec 9^th, 2011, 1:57pm

grrrrrr... you are sweeping I3, but I don't see where I3 is even used in the circuit.

Title: Re: 4-quad current multiplier
Post by loose-electron on Dec 9^th, 2011, 5:44pm

If hes at 3nA bias current, I want to see where he is on the bias curve of the device.

The circuit was spaghetti, I agree.

Title: Re: 4-quad current multiplier
Post by muffassir on Dec 10^th, 2011, 5:54am

Hi RobG and others ,

Here i am attaching my schematics as drawn in cadence..

Iin1 ,Iin2 are all annotated.Also Ibias=3nA is annotated in the below image.Vdd is set to 0.45V and Vss to -0.45V. Iin1=3nA and Iin2=3nA

The vdd is as inout to the FGMOS vs Id is plotted in the below image u can see the nFG7 to 2 are in this ...See left for counting the FGMOS serial number leftmost is nFG1 and so on to right.

Further for the waves of nFG1/D see below

I have also plotted the drain currents in each transistors verses the input current Iin1 from-3nA to 3nA.

See below image for the Iin1 Vs Id of nFG1.

If you find that the circuit should be manipulated ...please let me know where...???

Also The Iin1 Vs Iout from rightmost corner resistor(see schematic)..
is plotted.

Hope u all will suggest me some corrections if they are needed.
and let me know so that it will work as multiplier.
The capacitors used at the FGMOS gate inputs is of value 50pF each.

I have tried the circuit by removing the FGMOS capacitors and the associated ckt to make it purely MOS ckt i am getting the same results almost.

Title: Re: 4-quad current multiplier
Post by RobG on Dec 10^th, 2011, 6:38am

what paper is this based on? I still don't see how it can be anything but a mirror, but I remember a paper by Hassler that also confused me.

You should be able to plot that schematic as a postscript file and then convert it to pdf using ps2pdf. If you attach that instead of the screen shot it might help us as the screen shot is too small.

Title: Re: 4-quad current multiplier
Post by Vladislav D on Dec 10^th, 2011, 9:05am

Dude.... are there capacitors :) ? the gates are floating.....you d'better to connect the gates to something....

Title: Re: 4-quad current multiplier
Post by Vladislav D on Dec 10^th, 2011, 9:07am

Ask yourself what is the voltage at the gates at DC ? There is no DC path for the input current.
I'd suggest to start from a one-gate MOS and to get rid from the current mirrors that copying bias current. Who knows if transistors are in saturation there....and of course, capacitors should not be there

Title: Re: 4-quad current multiplier
Post by loose-electron on Dec 10^th, 2011, 9:44am

One more time:

Where are you on the bias curves for the transistors in the system?

The reason I am asking this question:

You will learn something if you go answer this question first.

Your DC bias situation needs to be resolved first, if the circuit architecture is not correct the bias will not be correct.

Hint! Hint!

Title: Re: 4-quad current multiplier
Post by RobG on Dec 10^th, 2011, 7:43pm

Vladislav D wrote on Dec 10^th, 2011, 9:05am:

Dude.... are there capacitors :) ? the gates are floating.....you d'better to connect the gates to something....

Vlad - The capacitors are floating gate capacitors so that is ok.

I think I'm catching on to how this works. There are two floating gates, so that means the gate voltage of the MOS is the sum of the voltages at the floating gate terminals. Thus Vgs ~ exp(Vgs1+Vgs2) which is what you need to multiplying action. At least I think so...

rg

Title: Re: 4-quad current multiplier
Post by Vladislav D on Dec 11^th, 2011, 6:41am

RobG wrote on Dec 10^th, 2011, 7:43pm:

Vladislav D wrote on Dec 10^th, 2011, 9:05am:

Dude.... are there capacitors :) ? the gates are floating.....you d'better to connect the gates to something....

Vlad - The capacitors are floating gate capacitors so that is ok.

OK. I got it. However, there is still a question how does a simulator interpret the potential at the gates at DC.
Muffassir, have u tried transient analysis? Also, I'd still recommend to get rid from current mirrors which copy Ibias for debugging purpose.

Title: Re: 4-quad current multiplier
Post by loose-electron on Dec 11^th, 2011, 11:38am

You have devices that have no DC bias.

Your definition of DC bias points has not been done with respect to transistor transfer curves.

The static currents are so small that they are probably below the valid bias points of the models, or under the error tolerance settings of the simulator.

Go resolve your DC bias situation first.

Title: Re: 4-quad current multiplier
Post by muffassir on Dec 14^th, 2011, 3:58am

RobG wrote on Dec 10^th, 2011, 6:38am:

what paper is this based on? I still don't see how it can be anything but a mirror, but I remember a paper by Hassler that also confused me.

yes u are correct its inspired from the Pual Hassler's paper.

Also i have tried to check the currents through each transistors.I changed the W/L ratios to get the currents in nFG1 and 2 to be Ib using trans analysis..now i am trying to get the Iin2 + Ib in nFG6 and 7 ...i think i am inserting Iin2 at the wrong place as the current is not getting added at the drain of nFG6 .Any suggestion in this regard is much appreciated.
Also i am new to cadence so soon i will upload the pdf file as suggested by you.

Title: Re: 4-quad current multiplier
Post by loose-electron on Dec 14^th, 2011, 11:32am

Are you familiar with bias curves for transistors or not?

Title: Re: 4-quad current multiplier
Post by loose-electron on Dec 14^th, 2011, 11:36am

RobG wrote on Dec 10^th, 2011, 7:43pm:

Vladislav D wrote on Dec 10^th, 2011, 9:05am:

Dude.... are there capacitors :) ? the gates are floating.....you d'better to connect the gates to something....

You don't want to use capacitive voltage division unless you have a method of defining the DC operating point.

The ratio floats and does not maintain itself reliably.

Title: Re: 4-quad current multiplier
Post by RobG on Dec 14^th, 2011, 12:41pm

loose-electron wrote on Dec 14^th, 2011, 11:36am:

You don't want to use capacitive voltage division unless you have a method of defining the DC operating point.

The ratio floats and does not maintain itself reliably.

They use tunneling to put the proper amount of charge on the gate. In theory this will never leak off so it will maintain. The floating cap pretty much acts like a battery in series with the gate. I've seen circuits published where the idea is used to trim opamp offsets or even provide voltage references. I (and others) have a hard time believing that the charge will remain constant over long periods of time, especially for commercial products that can't fail in the field after a year, but Hassler and others swear it will.

Title: Re: 4-quad current multiplier
Post by loose-electron on Dec 14^th, 2011, 4:36pm

RobG wrote on Dec 14^th, 2011, 12:41pm:

loose-electron wrote on Dec 14^th, 2011, 11:36am:

You don't want to use capacitive voltage division unless you have a method of defining the DC operating point.

The ratio floats and does not maintain itself reliably.

They may swear by it, but the rest of the world will swear at it.

Can't seem to get the OP to look at the bias curve location of things.
If you can not set the bias point up properly, everything else is a failure.
Also, currents stated are below default error tolerance of most simulators,
so I think hes looking at nonsense.
I tried.

Anybody got a PDF of this Hassler paper they can send me or post here?

Title: Re: 4-quad current multiplier
Post by muffassir on Dec 15^th, 2011, 12:20am

Hi all,

Well below is the paper i am implementing.Usually FGMOS papers are all influenced by the basic work carried out by P.Hasler,C.Driorio,C.Mead at Caltech. As said by RobG they use the tunneling concept. It seems that the RobG is familiar with the FGMOS .
The paper is in 350nm tech..and i am having 180nm tech..

Title: Re: 4-quad current multiplier
Post by muffassir on Dec 15^th, 2011, 12:22am

Hi all ,

Here is the Paper on the Multiplier ...Please see both the attchments .The previous and this one..

Title: Re: 4-quad current multiplier
Post by muffassir on Dec 15^th, 2011, 12:31am

Here is the paper by P.Hasler...
on FGMOS..

What u mean by bias curves...I have simulated the single FGMOS for dc analysis..Do you mean Id vs Vds curves..

Title: Re: 4-quad current multiplier
Post by RobG on Dec 15^th, 2011, 6:49am

loose-electron wrote on Dec 14^th, 2011, 4:36pm:

RobG wrote on Dec 14^th, 2011, 12:41pm:

loose-electron wrote on Dec 14^th, 2011, 11:36am:

You don't want to use capacitive voltage division unless you have a method of defining the DC operating point.

The ratio floats and does not maintain itself reliably.

They may swear by it, but the rest of the world will swear at it.

Yeah, I'm not ready to use it for analog. Sometimes it fails for digital! I did see a FG voltage reference in JSSC a few years ago and was hoping better information would come out on the long term stability of the method. It would be a great way to build a reference if stable.

Here are some more references from the red rag:
http://scholar.google.com/scholar?as_q=floating+gate&num=10&btnG=Search+Scholar&as_epq=&as_oq=&as_eq=&as_occt=any&as_sauthors=&as_publication=journal+of+solid+state+circuits&as_ylo=&as_yhi=&as_sdt=1.&as_sdtp=on&as_sdtf=&as_sdts=27&hl=en

Title: Re: 4-quad current multiplier
Post by loose-electron on Dec 15^th, 2011, 8:16pm

muffassir wrote on Dec 15^th, 2011, 12:31am:

Here is the paper by P.Hasler...
on FGMOS..

What u mean by bias curves...I have simulated the single FGMOS for dc analysis..Do you mean Id vs Vds curves..

That is anotheer way of describing a bias curve, yes, where are all of your transistors on their respective bias curves?

As for the paper, this is a research paper that does not give
reliability and retain-ability of the method.

Claims are based on somebody else's work:
"4uV over a 10 year period"

Show me real data for this, it might be in the other paper, but I doubt it.
Also, comments like using resistance values in simulation of 10E26 ohms
also raises red flags.

(that's simulator nonsense not real silicon)

Better credibility if in IEEE JSSC or IEEE EDS - not Database Symposium paper.
One EDS paper cited, but thats it.

I would not use the technique in anything that had to work reliaably