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Modeling >> Behavioral Models >> Verilog-A Statistical Variations
https://designers-guide.org/forum/YaBB.pl?num=1323681721

Message started by analog_power on Dec 12^th, 2011, 1:22am

Title: Verilog-A Statistical Variations
Post by analog_power on Dec 12^th, 2011, 1:22am

Hi,

I designed a model for hall element and everything works fine.
Now, I am on that state, where I want to put statistical parameters in it. I want that the parameters change with every simulation according to normal distribution. I want to use Monte Carlo simulation.

If I add "$rdist_normal($random,0,1)" to a resistor value, the value changes several times in a DC-sweep analysis, because the variable change at every look at this line.

When add this line in the initial block, then the simulator gets stacked.

How can I do that right?

Title: Re: Verilog-A Statistical Variations
Post by boe on Dec 12^th, 2011, 5:55am

Hi analog_power,
are you sure that your simulator allows $rdist_normal in a digital context (initial block)?

- B O E
PS: Which simulator do you use? What does "gets stacked" mean exactly?

Title: Re: Verilog-A Statistical Variations
Post by analog_power on Dec 12^th, 2011, 6:42am

I am not sure about that. Obviously it isn't allowed.
I am using spectre.
I am sorry, I tried to say that the simulation got stucked. I mean that there is no change in the progress bar.

Title: Re: Verilog-A Statistical Variations
Post by Frank Wiedmann on Dec 12^th, 2011, 6:54am

Are you talking about the digital initial block or the analog @(initial_step)? I don't see a reason why the latter shouldn't work and would consider it a bug if it doesn't.

Title: Re: Verilog-A Statistical Variations
Post by Forum Administrator on Dec 12^th, 2011, 10:20am

Try changing the transient method option to gear2only.

-Ken

Title: Re: Verilog-A Statistical Variations
Post by analog_power on Dec 13^th, 2011, 12:46am

I am talking about the @(initial_step block).
But is that the right way for making the model work with Monte-Carlo?

Ken,
what do you mean with gear2only ?

Title: Re: Verilog-A Statistical Variations
Post by analog_power on Dec 14^th, 2011, 5:44am

Now I know, what you mean with gear2only and it didn't change anything.

Title: Re: Verilog-A Statistical Variations
Post by analog_power on Dec 14^th, 2011, 7:30am

I still couldn't solve my problem.
Just an update:
I want to implement statistical Variations in my model. Independent of simulation mode. There should be different results even when I run manually simulations, without Monte Carlo or similar.

Has anybody an idea?

Title: Re: Verilog-A Statistical Variations
Post by Forum Administrator on Dec 14^th, 2011, 12:10pm

Saying the simulator is stuck does not really provide enough information. And given that the simple things did not work, it is time to try a little harder to figure out what is happening. The first question is: is the simulator really stuck, or is it just running very slowly. You might be able to figure this out by looking at the waveforms over time and see if they continue to grow. You might also have the waveform tool show you the time points and then explore what changed when the time steps dramatically shrunk. That might lead you to the cause of the problem. Alternatively, you can put the following line in a Verilog-A model:
$strobe("%0.15e", $abstime);
That will print the time to 15 digits, which should allow you to see whether time is progressing.

-Ken

Title: Re: Verilog-A Statistical Variations
Post by Marq Kole on Jan 18^th, 2012, 12:49am

Just some musings, but if you use $rdist_normal($random,0,1) it appears to be a bit overly random. Especially the DC might have an issue. Wouldn't it be better to use

Code:

parameter integer seed = 123456;
integer iseed;
analog initial iseed = seed;
analog begin
value = $rdist_normal(iseed, 0, 1);
...
end

Title: Re: Verilog-A Statistical Variations
Post by boe on Feb 14^th, 2012, 1:07am

Marq Kole wrote on Jan 18^th, 2012, 12:49am:

Just some musings, but if you use $rdist_normal($random,0,1) it appears to be a bit overly random. Especially the DC might have an issue. Wouldn't it be better to use

Code:

parameter integer seed = 123456;
integer iseed;
analog initial iseed = seed;
analog begin
value = $rdist_normal(iseed, 0, 1);
...
end

Marq,
unfortunately, the simulator performs the analog initial block for every MC run (at least mine does), so you get identical results for all runs.
- B O E

Title: Re: Verilog-A Statistical Variations
Post by jerome_ams on Jul 12^th, 2012, 2:23am

would VHDL be an option in your case? Some activities have been driven in Europe to develop an open source Statisitcal Package for both VHDL(AMS) and SystemC(AMS)
Cheers
J

Title: Re: Verilog-A Statistical Variations
Post by Geoffrey_Coram on Jul 18^th, 2012, 9:59am

I think Jerome_ams's post here:
http://www.designers-guide.org/Forum/YaBB.pl?num=1341703776

may be more appropriate to what analog_power wants to do.

Let the simulator set the random parameter values by using statistics blocks, and assign those values on the instance line of the Verilog-A model -- just like you would do for MC of a Spice built-in primitive.

Title: Re: Verilog-A Statistical Variations
Post by Hadi on Aug 7^th, 2012, 4:07pm

Hi everyone,

I simulated Hall element in COMSOL, but now, i want to design Hall element in Verilog-A.
I would appreciate if you could help me to design Hall element in Verilog-A...

Best,
Hadi