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Design >> Analog Design >> design of differential pair comparator
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Message started by lhlbluesky_lhl on Dec 13^th, 2011, 4:13am

Title: design of differential pair comparator
Post by lhlbluesky_lhl on Dec 13^th, 2011, 4:13am

in dynamic comparator design of differential pair, i have some questions here.

in the comp.rar file, fig1 is the schematic, fig2 is the design equation.

d=ID5/ID6, e=Vin/Vref, W1=W2, W3=W4.

but how to decide the value of ID5, ID6, d? because M5 and M6 are controled by clock signal Vclock, so the current of M5, M6 is difficult to set, so how to get an accurate ratio of d?

besides, k' is not a constant also, how to consider its value?

in my design, the value of ID5 and ID6 is changing with different size of (W/L)5 and (W/L)6, and the offset is different also for different size of M1~M4 and M5~M6, how to understand this?

please help me, and give me a clear explanation about the diferential pair comparator design, thanks.

Title: Re: design of differential pair comparator
Post by RobG on Dec 13^th, 2011, 6:17am

Can you please post a picture of your schematic instead of a rar file? You can post pdfs, pngs, etc.

Title: Re: design of differential pair comparator
Post by raja.cedt on Dec 13^th, 2011, 11:30am

hello,
refer this pap

A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC

Thanks,
Raj.

Title: Re: design of differential pair comparator
Post by lhlbluesky_lhl on Dec 14^th, 2011, 6:42am

hi, raja.cedt

can you send me the file of 'A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC'? i cannot download it from web, thanks.