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Design >> Analog Design >> VCO structure suggestion
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Message started by lunren on Dec 14^th, 2011, 9:34am

Title: VCO structure suggestion
Post by lunren on Dec 14^th, 2011, 9:34am

Hi All,

I am working on a PLL (almost every thing is done) at 912MHz. Now the customer want to change the frequency band to 2.4GHz. The preferred option is still using a ring OSC (trying to avoid inductor based VCO due to area and other concerns). I need some reference/suggestion for this time-limited design (tape out should not be delayed and I have no much time to do research and I don't have experience on such high frequency design). Any comments are welcome. By the way, here is the spec:
1) Frequency 2.4GHz
2) Quadrature output
3) as low as possible power consumption
4) 0.18um technology
5) 1.5V supply (1.8V supply regulated to 1.5V)
6) phase noise -85dBc/Hz @ 1MHz offset

Any one use Maneatis VCO working at 2~3GHz with 0.18um technology?

Thanks,

Lunren

Title: Re: VCO structure suggestion
Post by raja.cedt on Dec 14^th, 2011, 9:47am

hello,
four Ring oscillator will be good enough for those specs. As far as delay cell architecture
1. Delay interpolation architecture (refer razaavi text book), but power hungry

2. J-kim cell (A Low-Noise Fast-Lock Phase-Locked Loop with
Adaptive Bandwidth Control). This gives good Phase noise and if you add biasing current, you dont see much variation of frequency with respect to pvt

3. you can use meannatis also, but i have n't worked, but what i heard through people is at lower supply voltage it is very difficult to manage.

Thanks,
raj.

Title: Re: VCO structure suggestion
Post by loose-electron on Dec 14^th, 2011, 11:27am

I have used the Maneatis device with good success many times. Generally redesign the bias circuitry.

Consider running the ring oscillator at lower frequencies and using multiple phases from the ring to get the desired clocking rate.

Title: Re: VCO structure suggestion
Post by lunren on Dec 14^th, 2011, 2:02pm

raja.cedt wrote on Dec 14^th, 2011, 9:47am:

hello,
four Ring oscillator will be good enough for those specs. As far as delay cell architecture
1. Delay interpolation architecture (refer razaavi text book), but power hungry

Which book? He has many books and I didn't find it in his "Design of analog cmos integrated circuits"? Can you give me the book name?

Quote:

2. J-kim cell (A Low-Noise Fast-Lock Phase-Locked Loop with
Adaptive Bandwidth Control). This gives good Phase noise and if you add biasing current, you dont see much variation of frequency with respect to pvt

It seems a good one, I will do some research on this.

Quote:

3. you can use meannatis also, but i have n't worked, but what i heard through people is at lower supply voltage it is very difficult to manage.

I am also worry about this at lower supply. At 1.8V, should not a problem and at 1.5V I am not sure. Maybe Jerry can give some comments?

Title: Re: VCO structure suggestion
Post by raja.cedt on Dec 14^th, 2011, 2:08pm

hello,
you can refer integrated analog integrated ckts book vco chapter, but as i told before it is very power hungry. At 1.5 meannatis stage will give many problems at least when you are working PVT.

Thanks,
raj

Title: Re: VCO structure suggestion
Post by lunren on Dec 14^th, 2011, 2:13pm

loose-electron wrote on Dec 14^th, 2011, 11:27am:

Hi Jerry,

Do you think 1.5V supply for a 2.4GHz Maneatis device is doable? Can you give me some hints or reference on how to use low frequency multiple phases to get higher frequency clock?

Title: Re: VCO structure suggestion
Post by lunren on Dec 14^th, 2011, 2:15pm

raja.cedt wrote on Dec 14^th, 2011, 2:08pm:

I got it. Thanks a lot.

Title: Re: VCO structure suggestion
Post by loose-electron on Dec 14^th, 2011, 4:29pm

lunren wrote on Dec 14^th, 2011, 2:13pm:

loose-electron wrote on Dec 14^th, 2011, 11:27am:

Hi Jerry,

Do you think 1.5V supply for a 2.4GHz Maneatis device is doable? Can you give me some hints or reference on how to use low frequency multiple phases to get higher frequency clock?

Perhaps, but it depends on the threshold voltages
of the devices. It all scales down, but have to look at the speciifics
of the foundry process.

The poly phase method is pretty straightforward, think of it like this:
(illustrating using 9 delay cells)

Oscillator runs at 1 MHz
There are 9 1MHz square waves in your ring oscillator
Phase seperation of the 9 phases = 360 degrees/9 = 40 degrees
Take 9 clocks with 40 degrees phase difference
You have edge rates at 9MHz
Use some digital logic to combine the 9 signals to create
a signal which is 9X faster than the VCO frequency.

Thats the concept. I used this first way back in 0.5 micron CMOS
to get a SerDes system running at 2GB/sec.
We used 20 phases to get that to work with the slower transistors.

Title: Re: VCO structure suggestion
Post by lunren on Dec 14^th, 2011, 9:20pm

I see. If I am running VCO at 1.2GHz, then use frequency doubler (poly phase filter + Xor works for this), I should get 2.4Ghz. The only thing I am not sure is that the two output might not be quadrature outputs. I need to check it.