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Simulators >> Circuit Simulators >> Question for stb analysis
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Message started by ywguo on Dec 22^nd, 2011, 11:56pm

Title: Question for stb analysis
Post by ywguo on Dec 22^nd, 2011, 11:56pm

Hi Guys,

I have a testbench for stability of a regulator, which is shown in the following picture. The loop response is weird if the loop is broken in the feedback path. The loop phase started from 0 degree, increases 90 degree below 1 kHz. I get correct loop response if the loop is broken at the gate of MOS transistor. I know I have not broken all loops in the testbench if the loop is broken in the feedback path. However, I want to know if anybody can explain the weird behavior.

Thanks
Yawei

Title: Re: Question for stb analysis
Post by raja.cedt on Dec 23^rd, 2011, 5:49am

hello,
have you simulated through cadance .stb or by introducing LC filer? can you show the weird behavior and here only one loop it doesn't matter where you break i guess.

Thanks,
raj.

Title: Re: Question for stb analysis
Post by rfidea on Dec 23^rd, 2011, 10:02am

Hard to say without see the loop response or the schematic of your buffer. One guess is that you have two loops, that can give this 0 phase at low freqs and the increasing before it rolls of.

Title: Re: Question for stb analysis
Post by raja.cedt on Dec 23^rd, 2011, 10:15am

hello,
where do you see two loops, i guess the capacitor around the pass transistor he introduced for breaking the loop, if not i didnt understand the purpose of the capacitor.

thanks,
raj.

Title: Re: Question for stb analysis
Post by rfidea on Dec 24^th, 2011, 11:37am

I do not understand the capacitor either. In fact, I do not understand the discussion about breaking the loop at different locations. The stb will give you the same respons independet where the probe is inserted, as long as it is in the feedback loop.

I agree that there is no second loop in the drawn schematic. But since the amplifier is jut one block it is hard to know how it looks like inside. What I mean with two loops is that stb can give you this respons in there is two nested loops in the circuit. I had that problem in a CMFB loop once. The phase started at 0 degrees and then increased before rolling of.

Title: Re: Question for stb analysis
Post by raja.cedt on Dec 24^th, 2011, 12:18pm

hello,
i dont think he is using stb method, may be he is breaking loop by lc filter

thanks,
raj.

Title: Re: Question for stb analysis
Post by ywguo on Dec 25^th, 2011, 7:14pm

Hi Raj and rfidea,

I am sorry that I have not provide enough details like loop response. I did stb analysis. And the following are loop response. The first is wrong loop response when I insert iprobe in the feedback path.

Yawei

Title: Re: Question for stb analysis
Post by ywguo on Dec 25^th, 2011, 7:24pm

The second is a correct loop response when I insert iprobe at the gate of MOS transistor.

If I insert the iprobe in the feedback path, and set the resistance to 0 Ω in the red eclipse, I get correct loop response, too. It confuses me.

Title: Re: Question for stb analysis
Post by rfidea on Dec 26^th, 2011, 7:23am

Strange indeed! What happens if you remove the capacitor and replace the inductor with a short. At DC those changes should not change your circuit, loop gain and phase of 0 or 180 degrees should be the same.

Do you even then get "wrong" response with the probe in the feedback and "correct" response with the probe in series with the gate?

Title: Re: Question for stb analysis
Post by ywguo on Dec 26^th, 2011, 10:50pm

Hi rfidea,

That cap is a big compensation capacitor. So I do not remove it. That inductor is a part of bond wire model. The loop gain and phase do not change when I replace the inductor with a short.

The "wrong" response has nothing to do with the inductor. It does relates to the 0.1 Ω resistor. If I short that resistor, I get "correct" loop response when iprobe is in the feedback path.

Yawei

Title: Re: Question for stb analysis
Post by rfidea on Dec 27^th, 2011, 11:54am

It did not mean that you should remove the capacitor, or the inductor, from the design. It was just a test to see if and how the loop response at DC changes in such case.

Title: Re: Question for stb analysis
Post by ywguo on Dec 28^th, 2011, 7:24pm

I am sorry that the first picture is a simplified schematic that does not include all important details. Please have a look at the following schematics. At that time, I thought the 75 Ω resistor branch, which is a open-loop output, was not in the loop. In fact, it has around 18 dB gain for the blue loop if there is 0.1 ~ 0.2 Ω resistance in series to the ideal ground. I mean node 0 or gnd for the simulator when I say ideal ground. So I move iprobe to the opamp output as shown in the following picture. Now it is done.

Title: Re: Question for stb analysis
Post by rfidea on Dec 29^th, 2011, 1:24am

Ok, well done. Two loops can give you strange phenomena. Even your "wrong" response is true in some means. There is usually no danger to have 0 degree phase at low frequency as long as it increases to +90 before it rools off. But it is always good to know why it behaves as it does.

Title: Re: Question for stb analysis
Post by raja.cedt on Dec 29^th, 2011, 4:38am

hello rfidea,
i didn't understand why phase has to go 90 and come down to 0 for stable operation, even if it's fall from 0 without going to 90 it may stable only thing what we care is weather it is encircle -1 point or not..what do you say?

Thanks,
Raj.

Title: Re: Question for stb analysis
Post by rfidea on Dec 29^th, 2011, 1:10pm

It was probably a simplification from my side. If the open loop gain and phase behaves strange, which it was in this case and also in the one you suggest, I think one should check the stability with the complete Nyquist criteria. In that you should count the number of encircles of -1 but also the number of poles in the right half plane of the open loop transfer function.

If you do this for the "wrong" respose in this example you see that the transition from 0 degree to +90 degree is a pole in the RHPL for the open loop. But you will also find an encircle of -1. The signs are opposite so the number of poles in the RHPL for the closed loop is zero and the closed loop is then stable.

Title: Re: Question for stb analysis
Post by raja.cedt on Dec 29^th, 2011, 3:31pm

thank you.