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Design >> Mixed-Signal Design >> DNL and INL in incremental ADC
https://designers-guide.org/forum/YaBB.pl?num=1325075999

Message started by singh on Dec 28^th, 2011, 4:39am

Title: DNL and INL in incremental ADC
Post by singh on Dec 28^th, 2011, 4:39am

i have plotted output Vs input function for 2nd order ADC without missing any codes.
I just swept my DC input from 0 to 3 V and got my output codes for 14 bit ADC.

Now i wanted to plot DNL(in LSB) and INL(in LSB) plots with respect to input of ADC. for that i referred the code at below mentioned link.
http://inst.eecs.berkeley.edu/~n247/matlab_files/inldnl.m

now my doubt is
1) it asks 'input argument' as output of ADC,
% compute histogram
[counts,centers] = hist(x, min(x):delta:max(x));

but it gives DNl values in huge range like 5000 max and minimum 0..which is weird !!

2) it plots graph between DNL(in lSB) Vs bins but i need to plot it against input voltage...how to change that becoz while plotting the DNL values have more values then input?

3) in the following line of code,
title(sprintf('DNL and INL of %.1g Bit converter (from histogram testing)', ...
log2(N)));

why it always gives wrong value of converter resolution becoz N is based on length of DNL and DNL is based on counts ehich is very very high due to min(x):LSB:max(x) line in code? now how to rectify it in the given code ?
please help me regarding this

thanks in advance..

Title: Re: DNL and INL in incremental ADC
Post by ywguo on Dec 30^th, 2011, 7:26am

Hi Singh,

Did you feed a linear ramp signal on ADC input?
Would u pls provide a plot for the output code vs time/cycle?
Can attach the sampled data file?

Yawei