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Modeling >> Behavioral Models >> Verilog bus annotation using another bus
https://designers-guide.org/forum/YaBB.pl?num=1326294731

Message started by Ohn on Jan 11^th, 2012, 7:12am

Title: Verilog bus annotation using another bus
Post by Ohn on Jan 11^th, 2012, 7:12am

Hi,

I am trying to mux the n'th bit from a 256-bit wide bus, using the following method (which reminds C programming more than Verilog...):

module aaa (
input [255:0] y,
input [7:0] n,
output x
);

assign x = y[n];

endmodule

I have 2 cases:
1. When y is [255:0]
2. When y is [199:0] (obviously, not all 'n' values are acceptable)

The above code works in simulation, though something smells fishy.
Does anyone know what is the implementation of standard synthesis tools to this block?
What about case 2 - what would happen if 'n' gets the value of 200 and above? What value will be assigned to 'x' ?

Thanks,
Ohn