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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Common Source Amplifer Design Problem-simple but very confusing https://designers-guide.org/forum/YaBB.pl?num=1326352049 Message started by hai on Jan 11th, 2012, 11:07pm |
Title: Common Source Amplifer Design Problem-simple but very confusing Post by hai on Jan 11th, 2012, 11:07pm Hi, guys Recently, I have worked on some simulations about the CS amp design with Avago A10 process. The structure is fairly fundamental. A PMOS transistor on top works as an active load and a NMOS transistor at the bottom will provide the gm. The requirements are as below: The input and output DC voltage will be Vdd/2 strictly and the Vdd will vary from 2V to 5V for 10 steps. The bias current will vary from 2uA to 20uA with 10 steps. Under each bias current, the voltage will change from 2V to 5V. It will generate a bunch of simulations. My question is, under Id = 2uA for example, when I vary Vdd from 2V to 5V for each step, is that possible to make the bandwidth still go up? I have tried many ways but the BW always goes down. Thanks and regards Hai |
Title: Re: Common Source Amplifer Design Problem-simple but very confusing Post by raja.cedt on Jan 12th, 2012, 1:20am hello, for a simple CS amplifier, how change in vdd will lead to BW enhancement, because for given bias current the BW depends on the load cap and Vov of the input device, so try to it wont impact BW much. Thanks, Raj. |
Title: Re: Common Source Amplifer Design Problem-simple but very confusing Post by hai on Jan 12th, 2012, 8:17am raja.cedt wrote on Jan 12th, 2012, 1:20am:
Thanks for the reply, Raj The point is I don't use any load cap there. Therefore, only the fet's parasitic capacitance will work. My adviser keeps telling me that with Vdd increasing , the BW will definitely go up but my simulation results are always opposite. I try to maintain the gain to be almost the same and make the transistor size smaller under each Vdd with a give bias current. Theoretically, BW ∝ Id/Cl, here Id is constant so if I decrease Cl, the BW should go up. In my case, however, it always goes down. I am very confusing of that. Thanks Hai |
Title: Re: Common Source Amplifer Design Problem-simple but very confusing Post by ywguo on Jan 15th, 2012, 10:39pm Hi Hai ;), If there is a schematic, it would be more helpful for you. Yawei |
Title: Re: Common Source Amplifer Design Problem-simple but very confusing Post by raja.cedt on Jan 15th, 2012, 11:50pm hello hai, i don't know how Vdd changes your BW. Any how Please post the schematic. Seems you are beginner in analog so i would suggest you to refer Micro electronics book by razaavi or analog design essentials by Willy sansen. Thanks, Raj. |
Title: Re: Common Source Amplifer Design Problem-simple but very confusing Post by AnilReddy on Jan 19th, 2012, 1:39am hi, are you changing the input bias voltage of the stage along with the supply? Thanks Anil |
Title: Re: Common Source Amplifer Design Problem-simple but very confusing Post by tzg6sa on Jan 23rd, 2012, 5:16am Did you checked the output impedance? If vds increases the gds will decrease, i.e. the load resistance increases. This can decrease the BW at higher supply voltages. Could this be the case? |
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