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Design >> Analog Design >> About the supply voltage of an inverter in tsmc 65nm LP process
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Message started by easyads on Jan 12^th, 2012, 1:14am

Title: About the supply voltage of an inverter in tsmc 65nm LP process
Post by easyads on Jan 12^th, 2012, 1:14am

Hi
An inverter with minimum channel length(L=65nm) in tsmc 65nm LP process is designed. The recommended supply voltage of the inverter from tsmc is 1.2V.
(1) If the inverter is used as a static inverter, could the supply voltage vdd be more than 2.5V?
（2） IF the inverter is used as an clk buffer （Fclk=80MHz0), could the supply voltage vdd be more than 2.5V?

I have reversed an third party chip. In the chip, there is some inverters designed with minimum length(L=65nm), but the supply voltage of these inverter should be more than 2.5V by circuit analysis. Can this be reasonable?

Thanks .

Title: Re: About the supply voltage of an inverter in tsmc 65nm LP process
Post by raja.cedt on Jan 12^th, 2012, 1:37am

interesting...

Normally people tries to reduce the inverter supply, that to in 65nm i can't imagine 2.5V supply. I am sure for clock buffer no one use 2.5 and it will be around 1.2V. Some times inverters used as level shifters for high voltage to low voltage converter. May be this is the situation in your case.

Thanks,
Raj.