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Design >> Analog Design >> Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
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Message started by thechopper on Jan 12^th, 2012, 10:47am

Title: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by thechopper on Jan 12^th, 2012, 10:47am

I'm trying to find an answer on a rather general question that in my case showed up as a consequence of oscillation during start-up in an op-amp connected as a buffer:

- The input of my buffer goes connected to a voltage reference that overshoots while I'm ramping the power supply (say 5us ramp from 0-5v). A few us after the power supply voltage reaches 5v, the reference also settles
- The buffer shows an oscillation somewhere during the power supply ramp, such oscillation is sustained even when the input overshoot is gone and the average output value is equal to the input reference voltage.

I obviously checked the stability conditions around the operating point and the loop is by far stable. I also tried checking different op-points through which the buffer goes during power supply ramp but all of them are showing the loop is stable. It is clear I'm not finding the sweet spot at which the loop is not stable, but then the question arose:

Can a negative feedback loop that goes from a non-stable operating point - at which it oscillates - to a stable one and keep the oscillatory condition? The answer seems to be yes but it is not clear to me how that can happen.

I'm looking forward to see what you opinion is on this.
Thanks

Tosei

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by buddypoor on Jan 12^th, 2012, 11:28am

Hi Tosei,

I am very interested (and engaged) in all problems related to harmonic oscillations (for example, I am looking for a sufficient oscillation condition, which does not exist yet).
Therefore my question:
1.) Did you derive your observations from simulation or measurement?
2.) It would be best to show us the circuit; is it a simple opamp in unity gain configuration?
3.) Which opamp type?

buddypoor

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by raja.cedt on Jan 12^th, 2012, 11:37am

hello chooper,
yes, any -ve feedback will get you the stable operating point after some disturbance. did you check the with proper loadings about stability? Because some times breaking at wrong place or considering wrong loading gives you wired results..so please post schematic and oscillation waveforms...

Thanks,
Raj.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by Vladislav D on Jan 12^th, 2012, 11:44am

The first thing is to have a look at oscillation waveforms. Most often, current sources starts to oscillate since they have multiple fb loops. What kind of oscillation do u have? If this is low frequency and high amplitude oscillations, it will be definitely biasing circuit.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by thechopper on Jan 12^th, 2012, 1:21pm

buddypoor wrote on Jan 12^th, 2012, 11:28am:

Hi Buddypoor,

thanks for answering...I knew you were going to be interested on this one :). My answers

1) These are only simulation based results.
2) The schematic is no handy now (I could post it later) but yes, it is a simple unity gain configuration
3) The topology is a folded cascode, PMOS input diff pair one stage amp with a follower on the output to provide current capability

Best
Tosei

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by thechopper on Jan 12^th, 2012, 1:23pm

raja.cedt wrote on Jan 12^th, 2012, 11:37am:

Hi raja,

I assumed the same thing you are stating, but it does not to be the case for this one. Loading conditions are the ones the amplifier is to be used. And finally I do not break the loop but run stability analysis, which does not affect loading conditions.

Best
Tosei

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by thechopper on Jan 12^th, 2012, 1:26pm

Vladislav D wrote on Jan 12^th, 2012, 11:44am:

Hi Vladislav,

That's a good tip and I need to check them. The oscillation is around few MHz and about hundred mv or so. So I guess there is a chance that might be the case.
Anyway, I think I would need the biasing currents oscillating all the time to keep the oscillation on the buffer amplifier, otherwise I do not see how that could happen (to sustain oscillation around a stable point), which in the end is what I originally asked.

Best
Tosei

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by raja.cedt on Jan 12^th, 2012, 1:28pm

hello,
@Vladislav: ya..i know about bias oscillations, but how can you say that it is low frequency and high amplitude?

@ chopper: As Vladislav pointed out may be this is the issue and in folded cascode this is more prone problem called parasitic feedback which mainly comes by sharing pmos tail current bias and pmos current source in the load. If you do this, just for sanity check use separate bias for all transistors and check.

Thanks,
raj.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by raja.cedt on Jan 12^th, 2012, 1:31pm

hello chopper,

i forgot to say some my old exp
what do you mean by followers? is it source follower, then i am sure that is causing in presence of the load capacitance. Because i fed-up by this problems once. By connecting follower o/p to the op amp input follower see's big capacitive load.

Thanks,
Raj.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by Vladislav D on Jan 12^th, 2012, 2:13pm

raja.cedt wrote on Jan 12^th, 2012, 1:28pm:

hello,
@Vladislav: ya..i know about bias oscillations, but how can you say that it is low frequency and high amplitude?
Thanks,
raj.

When u design a current source u don't waste current on it and bias transistor with small currents. Moreover, large transistors are often used there. This implies that BW of feedback loops is low and, in case of stability issue, oscillation frequency is low since poles located at low frequency.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by thechopper on Jan 13^th, 2012, 4:32am

hi raja,

Thanks for the inputs. I was not aware of the parasitic feedback issue you pointed out. And yes, I was referring to a source follower, but again, the stability analysis around the operating point was indicating the loop was stable even with the source follower in place. I'll check the parasitic feedback and the bias current oscillations. It should be related to one of these.

Best
Tosei

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by raja.cedt on Jan 13^th, 2012, 4:48am

hello tosie,
yes you are correct, source follower stability problem will be detected by STB analysis. Regarding parasitic feedback please find the schematic where i faced this parasitic feedback

Thanks,
Raj.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by buddypoor on Jan 13^th, 2012, 5:12am

Hi Tosei,

did I understand well that oscillations could be observed only during ramping the supply voltage?
In this case, I wouldn't rely to much on circuit simulation because many models behave unrealistic for supply voltages that not in the "correct" range (as supposed by the model maker) - in particular when they are not constant.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by raja.cedt on Jan 13^th, 2012, 5:30am

hello buddypoor,
I have a Question, many times supply ramp means sweeping the supply from 0 to Vdd (many times vdd is the max), so if this is the case then there is no problem.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by buddypoor on Jan 13^th, 2012, 5:38am

raja.cedt wrote on Jan 13^th, 2012, 5:30am:

hello buddypoor,
I have a Question, many times supply ramp means sweeping the supply from 0 to Vdd (many times vdd is the max), so if this is the case then there is no problem.

Hi Raj,
what is your question? (My remark was for simulation only!).

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by thechopper on Jan 13^th, 2012, 7:13am

buddypoor wrote on Jan 13^th, 2012, 5:12am:

hi buddypoor,

Yes, you got it right: oscillations could be observed during ramping of supply voltage and were slowing damped till they fade away (as if the circuit was barely stable).
I agree also the models behave unrealistically under those type of transients, but I want to make sure it will not create any oscillation in real silicon.
Anyways, it seems from latest sims that the bias currents are the one to blame in my set up, which aligns with Vladislav suggestions.

Best
Tosei

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by thechopper on Jan 13^th, 2012, 7:14am

raja.cedt wrote on Jan 13^th, 2012, 4:48am:

Raj,

That is pretty much the same topology I have with the addition of the source follower I mentioned before.

Thanks
Tosei

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by raja.cedt on Jan 13^th, 2012, 11:23am

hello tosie,
if you are using same architecture then better use different bias for tail node as well as pmos load, if you get rid of oscillations then you are done. I doubt weather .stb will catch this or not.

Thanks,
Raj.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by despap on Jan 14^th, 2012, 12:49am

Problem statement i understood:

- Circuit is excited with supply ramp 0 -> VCC
- Circuit starts to show oscillations at the ouptut
- Oscillations starts to damp once supply stabilizes
- System dosent continue to oscillate for-ever

Couple of doubts here:
- When you did STB analysis, is it at stable supply?
- Are Load conditions are same for:
1. STB analysis
2. Supply ramp sim where osc are observed

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by raja.cedt on Jan 14^th, 2012, 2:38am

despap,
What is the meaning of "When you did STB analysis, is it at stable supply", because STB is for given operating point.

Thanks,
Raj.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by Vladislav D on Jan 14^th, 2012, 3:30am

raja.cedt wrote on Jan 14^th, 2012, 2:38am:

despap,
What is the meaning of "When you did STB analysis, is it at stable supply", because STB is for given operating point.

Thanks,
Raj.

And also for a one feedback loop, whereas in a circuit u have tens of loops

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by despap on Jan 14^th, 2012, 6:50am

@Raj
Yes..STB is at a operating point.

For this case i assume give operating point is at operating VCC. ( Vcc lets say 5V)

Where as oscillations are observed during supply ramp ( that is VCC < 5V), for which stability cant be commented unless its qualified for those supply values also, which exactly is the case for supply ramp.

Since STB can-not be performed ( rather not practical) for VCC ranging from 0 to 5V ( 5V here is representative), generally supply ramp transient verification is done to qualify the stability.

Correct me anything wrong.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by raja.cedt on Jan 14^th, 2012, 7:16am

hello despap,
yes you are correct, stb can be done only for a single operating point. But what i mean to say for example if a circuit is stable at 5V means if any disturbance occur to the ckt (may be slight change in the supply from 5V, or could be some common mode disturbance due to couple ) it has to restore it's previous state. So what i feel is if tosie verifies ckt stability at 5V it's okay to carry on.

But one thing i want to tell you is normally supply ramp will be done in transient to check is there any start-up issue (of course it make sense in +ve feedback ckts)

Thanks,
Raj.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by despap on Jan 14^th, 2012, 7:23am

@Raj
It will eventually stabilize with supply ramp. Oscillations will die down.

but with finite parasitics on VCC/GND paths..its always recommended to minimize oscillations during supply ramp.

Start-up is one check during supply ramp sims. But its not all. Ringing behavior should be looked for during supply ramp which actually gives how sturdy is a circuit.

with the presence of other circuits in the system, its potentially dangerous to have oscillations during supply ramp,which might actually end-up sustaining.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by raja.cedt on Jan 14^th, 2012, 8:14am

hello,
yes, you are talking for supply inductance and all, which will be present any how and they don't die may be because of continues switching or some thing else. Any how good discussion.

Thanks,
Raj.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by Dan Clement on Jan 16^th, 2012, 7:26pm

Where does the bias current for the amp and the follower come from?

You may need to delay or ramp the reference voltage until the bias currents are stable.

Are you sure the current densities are rationed properly in the folded cascode ota? You could look for systematic offset as a clue.

The simulator is telling you something. Proceed with caution.

Title: Re: Oscillation condition on neg fbk loop: can it be sustained at stable op-points?
Post by thechopper on Jan 19^th, 2012, 5:17am

Dan Clement wrote on Jan 16^th, 2012, 7:26pm:

Dan,

I checked the bias are properly rationed in the FC ota. I found the bias currents are the ones oscillating during VCC ramp. Actually, these currents are generated by the same voltage reference the ota is buffering: this means the ota buffers a voltage reference which seems to be affected by the loading effect the ota creates on it . This loading effect is two-fold: capacitive loading from ota input and resistive loading since bias currents are generated from voltage reference.

Bottom line: the ota is not the one oscillating, but the voltage reference it is buffering (and loading). This oscillation shows up while VCC is ramping up, and finally vanishes after a very long time, indicating an extremely low dumping factor.

Best
Tosei