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Design >> Mixed-Signal Design >> How do switches impact on the gain of switched-capacitor amplifier?
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Message started by Jacki on Jan 19^th, 2012, 9:44am

Title: How do switches impact on the gain of switched-capacitor amplifier?
Post by Jacki on Jan 19^th, 2012, 9:44am

Hello,

Now I am designing a fully differential switched-capacitor amplifier with gain of 2. At the sampling phase, both the sampling capacitor and hold capacitor are sampled. Then at the hold phase, all of the charges are transferred to hold capacitor. Cs=Ch=350fF. The basic specifications of the operational amplifier are as follows: gainbandwidth 600MHz, DC gain 73dB, phase margin 65 degree.

If I use ideal switches from Spectre analogLib, the PAC simulation is quite good, perfect 2 times amplification. But when I use the real switches (NMOS transistors), the PAC simulation will change as the device size is change.

I want to ask how to hand-calculate the PAC gain of SC-amplifier by using the device models, like Ron (on resistor of the switch), and fs (sampling frequency). Then I can estimate the transfer function of the SC-amplifier. Previously I have some experience on calculation of the gain of mixer and multiplier. I don't know if they are similar because for mixer and multiplier, they also work in the case "on" and "off", like a switch.

Any comments or reported references are highly appreciated.

Title: Re: How do switches impact on the gain of switched-capacitor amplifier?
Post by Jacki on Jan 19^th, 2012, 9:51am

One more question, if the accuracy of SC-amplifier is 10 bits, and if just consider the noise as the error source, how to calculate the noise impact? Should I integrated the noise, and see the ratio noise/signal amplitude, and then get the accuracy?

Also how does the switch impact on the bandwidth of PAC simulation. Because even using ideal switches, the -3 dB bandwidth of the SC-amplifier is quite different from the core opamp.

BTW: for the opamp simulation, the load is pure capacitor, 350fF between each output and ground.

Title: Re: How do switches impact on the gain of switched-capacitor amplifier?
Post by Jacki on Jan 20^th, 2012, 2:17am

In the simulation, through comparing the ideal switches and transistor switches, the main difference is the mode change between "off" and "on".
for an example, if I use ideal switches, the PAC gain is always 2 (magnitude). If I use transistor switches, the clock voltage, transistor size, and even the rise time and fall time of clock can influence the PAC gain. Of course if I turn the parameters, I can get very good curve for PAC simulation with magnitude of 2.

I want to ask how the switches influence on the switched-capacitor amplifier. Is there any calculation method (like building the models and calculate the gain by hand) to estimate the effect?

Thank you.

Title: Re: How do switches impact on the gain of switched-capacitor amplifier?
Post by Jacki on Jan 21^st, 2012, 2:14am

One question about the integrated noise for SC-amplifier, usually we talk the integration bandwidth is from 0 to infinite. Obviously, we don't need to integrated from 0Hz because we don't need to wait for years to see the noise. Is there any engineering rules for the integration bandwidth to calculate the integrated noise for SC-amplifier to estimate the accuracy?

Thanks.

Title: Re: How do switches impact on the gain of switched-capacitor amplifier?
Post by loose-electron on Jan 21^st, 2012, 7:05pm

Do some literature searches on switched capacitor circuits.

Lots of stuff out there
IEEE JSSC
is where I would start.

Title: Re: How do switches impact on the gain of switched-capacitor amplifier?
Post by Jacki on Jan 23^rd, 2012, 8:15am

Hello Loose-Electron,

I just want to know how to calculate the noise for SC-amplifier. Now I use spectre Pnoise to print the integrated output noise from 100Hz to 12.5MHz (fs = 25MHz), harmonics = 100. I find the thermal noise from the operational amplifier dominates the total integrated noise, it is 94%. The swiched-capacitor sampling noise is only 6%. Is it normal for SC-amplifier?

Even I modify the model to turn off the thermal noise of the transistors by setting the noise parameters to 0, it seems just the gate resistance and drain resistance can generate the integrated noise around 400uV, I think this value is too large.
nfalw = 0
nfblw = 0
nfclw = 0
fnto = 0
efo = 0

I want to ask if my integrated thermal noise of the operational amplifier normal?

BTW, I already turn off the flicker noise by modify the model.

Second, for the PAC gain simulation. When at charge transfer phase, the operational amplifier is working at the closed loop with the loop gain of 2. The open loop gain bandwidth of the opamp is 600MHz. Therefore, my boss told me the closed loop gain for the SC-amplifier should be 300MHz. But from my PAC simulation, the -3 dB corner for the SC-amplifier is just 12MHz. How to calculate the -3 dB frequency of the SC-amplifier?

Thank you.