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Design Languages >> Verilog-AMS >> how to save the output digital data in a file using Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1327238894

Message started by dfury on Jan 22^nd, 2012, 5:28am

Title: how to save the output digital data in a file using Verilog-A
Post by dfury on Jan 22^nd, 2012, 5:28am

Hi,
I have designed a CT delta-sigma modulator. I want to take the digital output into a text file so that I can process that data in MATLAB. I dont have a complete understanding of Verilog-A in the available cadence virtuoso suite of ver 5.1 . Could anyone share any model or code for this which I can add as a block.

I tried to use the following Spectre-AHDL code also from some reference

node [V, I] in, clk, out;
parameter real thres=1.65;
parameter integer dis_mod=1;
parameter string filename;
{
stream fptr;
integer count;
real inr;
real t=1e-9;
initial
{
fptr = $fopen(filename,"w");
count=0;
}
analog
{
inr = V(in);
if ($threshold( V(clk) - thres, 1 ))
{
$fstrobe(fptr,"%f \n", inr);
count=0;
}
V(out) <- $transition(inr,0,t,t);
}
}

but it shows me the following error

******************
DC Analysis `dcOp'
******************

Internal error found in spectre during DC analysis `dcOp'. Please run
`getSpectreFiles' or send the netlist, the spectre log file, the
behavioral model files, and any other information that can help
identify the problem to support@cadence.com.
"/home/sohaib/SGB25VD/skel/cdb/DSM_blocks/file_dump/ahdl/ahdl.def" 16:
Segmentation fault.

If someone could explain me this issue that would be helpful as well in solving my problem.

Regards

Title: Re: how to save the output digital data in a file using Verilog-A
Post by boe on Jan 24^th, 2012, 8:58am

Hi dfury,

afridi wrote on Jan 22^nd, 2012, 5:28am:

Hi,
...
but it shows me the following error

******************
DC Analysis `dcOp'
******************

Internal error found in spectre during DC analysis `dcOp'. Please run
`getSpectreFiles' or send the netlist, the spectre log file, the
behavioral model files, and any other information that can help
identify the problem to support@cadence.com.
"/home/sohaib/SGB25VD/skel/cdb/DSM_blocks/file_dump/ahdl/ahdl.def" 16:
Segmentation fault.

If someone could explain me this issue that would be helpful as well in solving my problem.

Regards

You have encountered a tool BUG. Contact Cadence support.
BTW, which tool versions do you use?

- B O E

Title: Re: how to save the output digital data in a file using Verilog-A
Post by dfury on Jan 24^th, 2012, 9:21am

How to find tool version? I am using Cadence Virtuoso 5.14

Title: Re: how to save the output digital data in a file using Verilog-A
Post by Geoffrey_Coram on Jan 24^th, 2012, 11:52am

afridi wrote on Jan 24^th, 2012, 9:21am:

How to find tool version?

Somewhere in the output before the error message, you should see the simulator name and version (Spectre 7.0.1_122, just to make up an example).

Title: Re: how to save the output digital data in a file using Verilog-A
Post by Forum Administrator on Jan 24^th, 2012, 2:54pm

Or you can run "spectre -W".

-Ken

Title: Re: how to save the output digital data in a file using Verilog-A
Post by dfury on Jan 24^th, 2012, 6:18pm

The version is Spectre 5.1.0

Title: Re: how to save the output digital data in a file using Verilog-A
Post by boe on Jan 25^th, 2012, 3:26am

Dfury,

afridi wrote on Jan 24^th, 2012, 6:18pm:

The version is Spectre 5.1.0

that is an ancient version. I suggest you change to a recent one.
- B O E

Title: Re: how to save the output digital data in a file using Verilog-A
Post by dfury on Jan 25^th, 2012, 4:20am

ok. You mean to upgrade the whole Cadence suite or just Spectre?

Do you think the error is there because this version is old?

Title: Re: how to save the output digital data in a file using Verilog-A
Post by boe on Jan 25^th, 2012, 7:29am

Dfury,

Quote:

Do you think the error is there because this version is old?

Updating spectre should be enough. You should use a MMSIM 10.x or MMSIM 11.x.
Knowing Cadence design support, they will tell you to update first anyway; also, this problem is probably already solved.

- B O E

Title: Re: how to save the output digital data in a file using Verilog-A
Post by dfury on Jan 25^th, 2012, 7:31am

Kindly could you direct me to the solution of my initial problem?

Title: Re: how to save the output digital data in a file using Verilog-A
Post by boe on Jan 25^th, 2012, 7:36am

Dfury,
I usually use Verilog-A, not SpectreHDL; but the code seems not too bad to me. However, I would expect the line

Code:

inr = V(in);

directly before the line

Code:

$fstrobe(fptr,"%f \n", inr);

- B O E

Title: Re: how to save the output digital data in a file using Verilog-A
Post by dfury on Jan 26^th, 2012, 5:54am

Hmmm, The error is still showing up. I guess there is some problem with its compiler.

Can anyone help me translate this into Verilog-A?

Title: Re: how to save the output digital data in a file using Verilog-A
Post by Geoffrey_Coram on Jan 27^th, 2012, 6:54am

Code:

`include "disciplines.vams"
module myoutput( in, clk, out);
inout in, clk, out;
electrical in, clk, out;

parameter real thres=1.65;
parameter integer dis_mod=1;
parameter string filename = "default.txt";

integer fptr;
integer count;
real inr;
real t;

analog begin
@(initial_step) begin
t=1e-9;
fptr = $fopen(filename,"w");
count=0;
end

inr = V(in);
@(cross( V(clk) - thres, 1)) begin
$fstrobe(fptr,"%f \n", inr);
count=0;
end

V(out) <+ transition(inr,0,t,t);

@(final_step) begin
$fclose(fptr);
end
end
endmodule

Title: Re: how to save the output digital data in a file using Verilog-A
Post by Geoffrey_Coram on Jan 27^th, 2012, 6:56am

As I was translating, I had a few questions:
1) Why is count always 0?
2) Why is t a variable instead of a parameter?

Title: Re: how to save the output digital data in a file using Verilog-A
Post by dfury on Jan 28^th, 2012, 2:11am

hmm I dont know exactly,
This code I read from this thesis liu.diva-portal.org/smash/get/diva2:19990/FULLTEXT01

Title: Re: how to save the output digital data in a file using Verilog-A
Post by boe on Jan 30^th, 2012, 5:27am

Geoffrey_Coram wrote on Jan 27^th, 2012, 6:56am:

As I was translating, I had a few questions:
1) Why is count always 0?
2) Why is t a variable instead of a parameter?

As already mentioned, I would expect

Code:

@(cross( V(clk) - thres, 1)) begin
inr = V(in);
$fstrobe(fptr,"%f \n", inr);
count=0;
end

instead of

Code:

inr = V(in);
@(cross( V(clk) - thres, 1)) begin
$fstrobe(fptr,"%f \n", inr);
count=0;
end

Anyway, neither code should cause internal errors on current Spectre versions.
- B O E

Title: Re: how to save the output digital data in a file using Verilog-A
Post by Geoffrey_Coram on Feb 1^st, 2012, 10:14am

boe -
Well, that's an interesting question: is the output supposed to change only on the clock ( inr = V(in) inside the cross event block, as you expect) or always.

Because there's a transition filter, I guess I would tend to agree with you; it's a bad idea to put a transition on a continuous signal, but we don't actually know anything about what's connected to "in"

But this thread is mostly about writing the digital data to a file, so I wasn't paying attention to that.

Title: Re: how to save the output digital data in a file using Verilog-A
Post by Forum Administrator on Feb 1^st, 2012, 3:07pm

Never ever do the following:

Code:

inr = V(in);
V(out) <- $transition(inr,0,t,t);

In other words, the first argument to the transition function should never be a continuous function of an electrical signal, even if you believe the electrical signal is constant. In contrast, the following is perfectly fine:

Code:

@(cross( V(clk) - thres, 1))
inr = V(in);
V(out) <- $transition(inr,0,t,t);

The difference her is that inr is set in an event block and so cannot vary continuously with V(in).

Many times I have seen code that looks like the following:

Code:

if (...)
val = 1;
else
val = 0;
V(out) <+ transition(val*V(vdd), 0, 10n);

Such code leads to heartbreak and misery. The problem is that V(vdd) is computed by the simulator, and can change slightly from time point to time point (often time these changes are at the attovolt level). Those changes will activate the transition function, which limits the time steps and slow the simulation. You should instead use:

Code:

if (...)
val = 1;
else
val = 0;
V(out) <+ V(vdd)*transition(val, 0, 10n);

-Ken

Title: Re: how to save the output digital data in a file using Verilog-A
Post by afridi on Feb 7^th, 2012, 3:11am

Thank you everyone for your insight.

The verilog-A code gives error at

Code:

parameter string filename ="default.txt"

when I remove the word "string" it works. any idea what it is?

Title: Re: how to save the output digital data in a file using Verilog-A
Post by afridi on Feb 7^th, 2012, 4:26am

boe wrote on Jan 30^th, 2012, 5:27am:

Geoffrey_Coram wrote on Jan 27^th, 2012, 6:56am:

As I was translating, I had a few questions:
1) Why is count always 0?
2) Why is t a variable instead of a parameter?

As already mentioned, I would expect

Code:

@(cross( V(clk) - thres, 1)) begin
inr = V(in);
$fstrobe(fptr,"%f \n", inr);
count=0;
end

instead of

Code:

inr = V(in);
@(cross( V(clk) - thres, 1)) begin
$fstrobe(fptr,"%f \n", inr);
count=0;
end

Anyway, neither code should cause internal errors on current Spectre versions.
- B O E

What I understand is,that the inr in the first case would save the its values after the clock voltage crosses over the threshold, but in the second case it will save the value before the clock voltage?

Then is the second approach completely wrong? or their effect is the same?
Regards

Title: Re: how to save the output digital data in a file using Verilog-A
Post by boe on Feb 7^th, 2012, 10:04am

Afridi,

afridi wrote on Feb 7^th, 2012, 4:26am:

...
What I understand is,that the inr in the first case would save the its values after the clock voltage crosses over the threshold, but in the second case it will save the value before the clock voltage?

No, in the first case inr changes at every simulator time step, while in the other case it changes only at clock edge. This will effectively cause the output V(out) to be sampled in the second case. See also Geoffrey's comment (reply #16).

Quote:

Then is the second approach completely wrong? or their effect is the same?

The difference is in V(out) and how efficiently the output signal is simulated. See Ken's post for the explanation why. If you remove the contribution statement to V(out), both cases should create the same output file.

afridi wrote on Feb 7^th, 2012, 3:11am:

The verilog-A code gives error at

Code:

parameter string filename ="default.txt"

when I remove the word "string" it works. any idea what it is?

Apparently (your version of) the simulator does not support this syntax.
- B O E

Title: Re: how to save the output digital data in a file using Verilog-A
Post by Geoffrey_Coram on Feb 7^th, 2012, 12:27pm

"string" was not part of Verilog-AMS in the beginning, but some simulators allowed you to specify a string literal (something in "quotes") -- digital Verilog allowed some conversion between characters and 8-bit "reg" data values. Since "string" wasn't a keyword, you couldn't use it, but Verilog has some automatic parameter type determination, so you could specify a string literal as the default value and this would effectively make the parameter of type string.

Title: Re: how to save the output digital data in a file using Verilog-A
Post by boe on Feb 8^th, 2012, 3:39am

Geoffrey,
however, recent versions of the Cadence Verilog-A Language Reference contain this parameter string syntax. So current versions of Spectre should understand this.

- B O E

Title: Re: how to save the output digital data in a file using Verilog-A
Post by Geoffrey_Coram on Feb 9^th, 2012, 8:39am

Ah, but in another thread, Afridi admitted to running 5.10 (and was admonished there to get a more recent version).