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Design >> Mixed-Signal Design >> Seal Ring in IC
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Message started by ic_engr on Jan 23^rd, 2012, 6:37am

Title: Seal Ring in IC
Post by ic_engr on Jan 23^rd, 2012, 6:37am

Hello Everyone,

I would like to get some papers or information on the importance of Seal Ring in IC Design. What does seal ring impact and what are the draw backs of not havign sealring in an IC.

I saw a link on google but does not seem to work:

www.ics.ee.nctu.edu.tw/~mdker/.../SHChen_Ker_JMR_Sept_2005.pdf

Any information is appreciated.

Regards

ic_engr

Title: Re: Seal Ring in IC
Post by vivkr on Jan 25^th, 2012, 7:58am

I don't have links to papers but I would have thought that Google would get you enough hits there.

The seal ring is used to isolate the active silicon area from the external environment, basically from humidity. If moisture creeps into your die over time, then it may cause corrosion and change impedances between the various nodes on your chip. This would be a big problem which would likely cause your design to malfunction sooner or later.

I cannot imagine any reason not to use the seal ring. There are some cases where people are trying to make a really small ASIC and cutting down the cost but even then, the seal ring is quite a small thing and it saves you the trouble of having to worry about what might happen if you didn't have it.

By the way, depending on your process and quality flow, you may not even be allowed to do anything like leaving out the seal ring.

Vivek

Title: Re: Seal Ring in IC
Post by Dan Clement on Jan 26^th, 2012, 4:53am

Some companies also use the seal ring as an ESD discharge bus.

Title: Re: Seal Ring in IC
Post by loose-electron on Jan 26^th, 2012, 8:09pm

Seal ring usually gets tied to a lot of substrate taps
and then ends up getting tied to I/O ring ground.