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Design Languages >> Verilog-AMS >> new to verilog ams
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Message started by thomasT on Jan 27^th, 2012, 5:16am

Title: new to verilog ams
Post by thomasT on Jan 27^th, 2012, 5:16am

what does the below mentioned statements signify:

@(above(V(ina) - VTH)) ...does it means V(ina)> VTH then execute ??

@(cross(V(clk_en) - VTH, +1)) what is the meaning of this statement?

please also give some reference to a good book to learn. but please explain these two with athe above example.

thanks

Title: Re: new to verilog ams
Post by Geoffrey_Coram on Jan 27^th, 2012, 6:58am

The best book to read is Ken's "Designer's Guide to Verilog-AMS"

But your questions can be answered by simply reading the Language Reference Manual (LRM), which is available from this site.

Title: Re: new to verilog ams
Post by dfury on Jan 28^th, 2012, 2:05am

Quote:

@(cross(V(clk_en) - VTH, +1)) what is the meaning of this statement?

It means when the V(clk_en)-VTH is a positve change it will cause the subsequent statements to occur.

I dont understand the first one.

Title: Re: new to verilog ams
Post by Geoffrey_Coram on Jan 30^th, 2012, 10:49am

@(above) also works during a dc analysis (including time=0); if V(clk_en) > VTH at t=0, the cross event will not be triggered (until the next time clk_en crosses).