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Design Languages >> Verilog-AMS >> Delay block in Verilog-A
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Message started by dfury on Jan 28^th, 2012, 3:53am

Title: Delay block in Verilog-A
Post by dfury on Jan 28^th, 2012, 3:53am

Hi,

Can anyone tell me or direct me to some idea about how to design a delay block in Verilog-A which can give a variable delay in a path of an actual circuit.

I intend to simulate the effect of delay on the circuit characteristics without disturbing the currents or voltages of the path but just introducing the delay .

Title: Re: Delay block in Verilog-A
Post by boe on Jan 30^th, 2012, 5:33am

afridi,
Read the LRM (Language Reference Manual) or your tool documentation.
- B O E

Title: Re: Delay block in Verilog-A
Post by Forum Administrator on Jan 30^th, 2012, 9:15am

Specifically, I recommend you look at the absdelay() function.

-Ken