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Design Languages >> Verilog-AMS >> Convergence in TRAN verilogA
https://designers-guide.org/forum/YaBB.pl?num=1327926416

Message started by fabian on Jan 30^th, 2012, 4:26am

Title: Convergence in TRAN verilogA
Post by fabian on Jan 30^th, 2012, 4:26am

Hi Every,

I am reading more than I could help much.

I am having convergences issue with veriloga model and the output log is quite unexplicit to find out the reasons or pointing me to the bad circuit modelled. May I have one of you helping me or giving some tips on the following code? Any advice to avoid convergence issue are welcome. I have simply the code get to the point.

The bias block is:
`include "constants.vams"
`include "disciplines.vams"

module bgBias_simple(vdd, ibp, gnd);
input vdd, gnd;
output ibp;

electrical vdd, gnd, ibp;
parameter real ibias = 100n;

analog begin
if (V(vdd, gnd) > 1)
I(vdd, ibp) <+ ibias + ($temperature - 300.15) * 0.4n ;
else
I(vdd, ibp) <+ 1.0p;
end
endmodule

The loaded block is:
`include "constants.vams"
`include "disciplines.vams"

module regulator_simple(vdd, ibp, enBat, gnd);
input vdd, ibp, enBat, gnd;
electrical vdd, ibp, enBat, gnd;

real id;

analog begin

@(cross((V(ibp, gnd) + I(ibp, gnd)), 0));
id = 0.1p * (limexp(V(ibp, gnd)/$vt)-1.0);
if (V(enBat, gnd) > 0.0)
begin
if ((V(ibp, gnd) + I(ibp, gnd)) > 0)
I(ibp, gnd) <+ id;
else
V(ibp, gnd) <+ 0.0;
end
else
I(ibp, gnd) <+ 0.0;

end
endmodule

So when I connect the both blocks and simulate I got a clear DC simulation but the transient crashed with the following statement:

Zero diagonal found in Jacobian at `net4' and `net4'.
Reordering Jacobian.
.........
Trying `homotopy = ptran' for initial conditions..
Trying `homotopy = arclength' for initial conditions.

Error found by spectre during IC analysis, during transient analysis `tran'.
ERROR (SPECTRE-11005): Matrix is singular (detected at `net4').
ERROR (SPECTRE-16385): There were 7 attempts to find the DC solution. In some of those attempts, a signal exceeded the blowup limit of its quantity. The last signal that failed is V(net4) = 1 GV, for which the quantity is `V' and the blowup limit is (1 GV). It is possible that the circuit has no DC solution. If you really want signals this large, set the `blowup' parameter of this quantity to a larger value.
ERROR (SPECTRE-16080): No DC solution found (no convergence).

The net4 is the net connecting ibp.regulator_simple to ibp.bgBias_simple. Please any helps will be more than welcome.

Thanks in advance,

Title: Re: Convergence in TRAN verilogA
Post by boe on Jan 30^th, 2012, 5:30am

fabian,
hard switching of currents, and switching between voltage and current sources is not recommended. It often causes convergence issues.
- B O E

Title: Re: Convergence in TRAN verilogA
Post by fabian on Jan 30^th, 2012, 6:03am

Dear BOE,

Do you mean that I should not use 0.0 value?
Do you mind may be pointing me to an example illustrated what you recommend? I am glad to hear any advices on convergence.

Best regards,
Fabian

Title: Re: Convergence in TRAN verilogA
Post by boe on Jan 31^st, 2012, 2:43am

Dear Fabian,

fabian wrote on Jan 30^th, 2012, 6:03am:

Dear BOE,

Do you mean that I should not use 0.0 value?

I mean that when the conditions in your if statements change value, your code changes values (and even topology) abruptly.

Quote:

Do you mind may be pointing me to an example illustrated what you recommend? I am glad to hear any advices on convergence.

E.g. (assuming temperature does not change continuously)
Code:

...
parameter real ibias = 100n;
real ib;
analog begin
if (V(vdd, gnd) > 1)
ib = ibias + ($temperature - 300.15) * 0.4n ;
else
ib = 1.0p;
I(vdd, ibp) <+ transistion(ib, 0, 1n);
end
endmodule

It would be even better to use an above (or cross) event.
- B O E

Title: Re: Convergence in TRAN verilogA
Post by boe on Jan 31^st, 2012, 3:36am

Dear Fabian,

fabian wrote on Jan 30^th, 2012, 4:26am:

...
The loaded block is:
`include "constants.vams"
`include "disciplines.vams"

module regulator_simple(vdd, ibp, enBat, gnd);
input vdd, ibp, enBat, gnd;
electrical vdd, ibp, enBat, gnd;

real id;

analog begin

@(cross((V(ibp, gnd) + I(ibp, gnd)), 0));
id = 0.1p * (limexp(V(ibp, gnd)/$vt)-1.0);
if (V(enBat, gnd) > 0.0)
begin
if ((V(ibp, gnd) + I(ibp, gnd)) > 0)
I(ibp, gnd) <+ id;
else
V(ibp, gnd) <+ 0.0;
end
else
I(ibp, gnd) <+ 0.0;

end
endmodule

See e.g. http://www.designers-guide.org/Forum/YaBB.pl?num=1211713371/4#4.
- B O E

Title: Re: Convergence in TRAN verilogA
Post by fabian on Jan 31^st, 2012, 5:07am

Hi BOE,

I saw the current limit voltage regulator but it is changing between a current and a voltage which is what you do not recommend to do, is not it?

I simplify using a tanh function for the current source such as:
module bgBias_simple(vdd, ibp, gnd);
input vdd, gnd;
output ibp;

electrical vdd, gnd, ibp;
parameter real ibias = 100n;

analog begin
I(vdd, ibp) <+ ibias * tanh(V(vdd, gnd)) + ($temperature - 300.15) * 1.0n ;

end
endmodule

and the load circuit which is now using your recommendation:
module regulator_simple(vdd, ibp, enBat, gnd);
input vdd, ibp, enBat, gnd;
electrical vdd, ibp, enBat, gnd;
parameter real vth_logic=0.5;
real id;

analog begin
if (V(enBat, gnd) > vth_logic)
id = 0.1p * (limexp(V(ibp, gnd)/$vt)-1.0);
else
id = 0.1n;
I(ibp, gnd) <+ transition(id, 0, 1n);
end
endmodule

I have no problem for DC sweep simulation but it can not find the dcOp for the TRAN simulation. I am using transition function to avoid sharp transition for convergence but it is still not converging.

Do you have any clue how to solve the problem as I do not see why he does not have issue with DC but cannot converge with TRAN?

Thanks for your help in advance,

Title: Re: Convergence in TRAN verilogA
Post by boe on Jan 31^st, 2012, 6:38am

Fabian,
if you connect the pins ibp of your bias and your regulator, you connect two current sources. If V(enBat, gnd) <= vth_logic the currents are probably not equal, so you need some path for the current in this case.
It is possible to change between a current source and a voltage source; however, you need to be very careful to avoid discontinuities (the code proposed does this). I prefer to use a source with dynamic source impedance (changed by a transition filter) wherever possible.
- B O E

Title: Re: Convergence in TRAN verilogA
Post by fabian on Jan 31^st, 2012, 7:09am

Dear BOE,

Thanks for your avices.

1. if you connect the pins ibp of your bias and your regulator, you connect two current sources. If V(enBat, gnd) <= vth_logic the currents are probably not equal, so you need some path for the current in this case.

This part is a bit confusing as when I replace this if statement by:
id = 0.1p * (limexp(V(ibp, gnd)/$vt)-1.0);
I(ibp, gnd) <+ id;

I have got no problem and I believe at t=0s, the two current sources are not equal but I am able to converge without any issue. Do you understand this or am I missing something here?

2. It is possible to change between a current source and a voltage source; however, you need to be very careful to avoid discontinuities (the code proposed does this). I prefer to use a source with dynamic source impedance (changed by a transition filter) wherever possible.

Could you share with me an example of a dynamic source impedance change by a transition filter? sorry to ask basic stuff here.

Thanks for your help

Title: Re: Convergence in TRAN verilogA
Post by boe on Jan 31^st, 2012, 9:12am

Fabian,

fabian wrote on Jan 31^st, 2012, 7:09am:

...
This part is a bit confusing as when I replace this if statement by:
id = 0.1p * (limexp(V(ibp, gnd)/$vt)-1.0);
I(ibp, gnd) <+ id;
...

This describes a "nonlinear resistor" (I(ibp, gnd) = f(V(ibp, gnd)) [OK, actually, a diode], not an ideal current source.

Quote:

...
Could you share with me an example of a dynamic source impedance change by a transition filter? sorry to ask basic stuff here.

E.g. (enabled 1.2V regulator):

Code:

...
real res = 1G;
analog begin
if (V(enable, gnd) > vth_logic)
res = 1; // enabled
else
res = 1G; // off

V(out1, gnd) <+ 1.2;
I(out, out1) <+ V(out, out1) * limexp(transition(ln(1/res), 0, 1n));
end

Note: this is to show the basic idea. You should use a cross or above event to check for level changes in the enable signal. BTW, for efficiency reasons you should use an implementation with only one analog (electrical) node.

- B O E

PS: Note that the transition filter input should change at discrete time points only. See LRM (Language Reference Manual) or tool vendor documentation. So this is not recommended:

Code:

id = 0.1p * (limexp(V(ibp, gnd)/$vt)-1.0);
I(ibp, gnd) <+ transition(id, 0, 1n);

Edit: Changed code to Verilog-A syntax.

Title: Re: Convergence in TRAN verilogA
Post by Forum Administrator on Jan 31^st, 2012, 1:26pm

In your original post, the error message pointed you directly to the problem: net4. When the simulator says the 'matrix is singular' it means that there is a floating node or a loop of shorts. And if you look at net for, you are driving it with a current source and when you are in current limiting mode you are loading it with a current source. In this situation, the voltage of net4 is undefined. The end result, the matrix is singular. At the very least you need to add gmin to one of those terminals.

-Ken

Title: Re: Convergence in TRAN verilogA
Post by fabian on Feb 1^st, 2012, 4:33am

Dear Ken and BOE,

Thanks for your support. I am not able to verify the solution from BOE as the compiler does not understand $ln.

Regarding the gmin solution, I am not understand what do you mean? Are you saying that I need to add a large resistance to ground? Do you have an example of implementation?
Thanks in advance

Title: Re: Convergence in TRAN verilogA
Post by boe on Feb 1^st, 2012, 6:03am

Dear Fabian,

fabian wrote on Feb 1^st, 2012, 4:33am:

Thanks for your support. I am not able to verify the solution from BOE as the compiler does not understand $ln.

$ln is digital Verilog/Verilog-AMS syntax for natural logarithm; in Verilog-A use ln instead.

Quote:

Regarding the gmin solution, I am not understand what do you mean? Are you saying that I need to add a large resistance to ground?

Adding a large resistor to high-impedance nodes tends to improve convergence.

- B O E

Title: Re: Convergence in TRAN verilogA
Post by Forum Administrator on Feb 1^st, 2012, 8:56am

Gmin is a large valued resistor, traditionally 1TΩ. You can add it either to the bias or the regulator blocks. To add it to the bias block, add

Code:

I(vdd, ibp) <+ V(vdd, ibp)/1T;

to the end of the analog block. To add it to the regulator, change

Code:

I(ibp, gnd) <+ id;

to

Code:

I(ibp, gnd) <+ id + V(ibp, gnd)/1T;

-Ken

Title: Re: Convergence in TRAN verilogA
Post by fabian on Feb 1^st, 2012, 9:50am

Thanks to both of you. I converge now.
Fabian