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Design >> RF Design >> voltage leakage in VCO's switching capacitor
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Message started by YCY on Feb 2^nd, 2012, 1:23am

Title: voltage leakage in VCO's switching capacitor
Post by YCY on Feb 2^nd, 2012, 1:23am

Hi,

I am designing an RF VCO with switching capacitors, whose oscillation frequency is around 3GHz.
The switching cap cell in the off-state is simplified as:

The voltage V_D is precharged to a value near 0.8 V to assure the NMOS is off when its gate is switched to ground.
However, when I do the transient analysis and set a very long stop time, say 10us,
the voltage V_D starts to drop to near 0V.
I don't think the voltage drop comes from the leakage current of the NMOS, if so,
the voltage should be pulled up to 1.2V but not drop to 0V.

I also find that the speed of voltage drop is related to the accuracy of transient analysis.
The simulation results is shown below
(liberal, moderate, conservative are the errpreset, pointlocal is conservative with relref=pointlocal, reltol=1e-5 is conservative with reltol=1e-5
The dropping speed is liberal>moderate>conservative>pointlocal>reltol=1e-5)

I cannot figure out how the accuracy setting affects this simulation result.
Does anybody have any idea about this phenomenon?
Thanks in advance.

YCY

Title: Re: voltage leakage in VCO's switching capacitor
Post by boe on Feb 2^nd, 2012, 5:01am

YCY,
The simulator tries to solve the current equation at node V_D to an accuracy given by the accuracy settings.
Any error in the difference current (transistor vs. cap) will change the average voltage across your cap. These errors get smaller when you tighten accuracy requirements, so your charge loss gets smaller.

- B O E

Title: Re: voltage leakage in VCO's switching capacitor
Post by loose-electron on Feb 2^nd, 2012, 2:21pm

boe wrote on Feb 2^nd, 2012, 5:01am:

Agreed with Boe.

Also, you need to recognize that a capacitor has leakage (outside the simulator accuracy, this is a different issue) so do not expect to precharge a capacitor, and have it maintain that voltage for long periods of time.

Title: Re: voltage leakage in VCO's switching capacitor
Post by YCY on Feb 2^nd, 2012, 5:47pm

boe wrote on Feb 2^nd, 2012, 5:01am:

Hi, B O E,

Thank you so much for your reply.
However, I am also curious if it is possible to quantify the relation between the accuracy and discharge time?
For example, if iabstol=1pA, and the cap=100fF,
then t_dis= 0.6V*100f/1pA=60ms is needed to disharge the cap from 0.6V to 0V,
but the result is obviously wrong.
So, I just wonder if there exists equations that can
specifically describe the relations among reltol, iabstol, C, dV, and t_dis.

Thanks again,
YCY

Title: Re: voltage leakage in VCO's switching capacitor
Post by YCY on Feb 2^nd, 2012, 6:03pm

loose-electron wrote on Feb 2^nd, 2012, 2:21pm:

boe wrote on Feb 2^nd, 2012, 5:01am:

Hi, loose-electron

Thanks very much for your reply.
I also doubted the cap leakage in the begging,
so I replaced it with an ideal one.
Yet the leakage remains the same.

Besides, all the dc voltages in the circuit are much higher than 0V.
Thus I used to think that even leakage exists, V_D will be charged to a higher voltage but not pulled down to 0V.
But the simulation result shows the opposite.

regards,
YCY

Title: Re: voltage leakage in VCO's switching capacitor
Post by YCY on Feb 2^nd, 2012, 6:35pm

BTW, I also found a very unreasonable result.
The current flowing out of the cap (which is an ideal one)
is not equal to that flowing into the NMOS and has a very large difference.
Here are the schematic and the simulation result.
(I probed the terminal Minus of the cap, and D of the NMOS. There is not any other component connected to this node)

It obviously violates KCL, does anyone know why?

Thanks,
YCY

Title: Re: voltage leakage in VCO's switching capacitor
Post by boe on Feb 3^rd, 2012, 6:19am

YCY,

YCY wrote on Feb 2^nd, 2012, 5:47pm:

...
For example, if iabstol=1pA, and the cap=100fF,
then t_dis= 0.6V*100f/1pA=60ms is needed to disharge the cap from 0.6V to 0V,
but the result is obviously wrong.
So, I just wonder if there exists equations that can
specifically describe the relations among reltol, iabstol, C, dV, and t_dis.

Note that typically reltol*i >> iabstol. Error limit is abs(i)*reltol + iabstol, where i is influenced by relref.

Quote:

Check the gate and bulk currents for capacitive coupling from node V_D to gate/bulk. You will find that they are not part of the drain current.

- B O E

Title: Re: voltage leakage in VCO's switching capacitor
Post by boe on Feb 3^rd, 2012, 7:22am

YCY wrote on Feb 2^nd, 2012, 6:03pm:

Hi, loose-electron

Thanks very much for your reply.
I also doubted the cap leakage in the begging,
so I replaced it with an ideal one.
Yet the leakage remains the same.

Cap leakage should not depend on simulation accuracy settings.
Still it is -- as loose-electron pointed out -- important for some circuits (such as this example). YMMV, but unfortunately it tends to be missing in cap models.
- B O E

Title: Re: voltage leakage in VCO's switching capacitor
Post by YCY on Feb 3^rd, 2012, 8:00am

boe wrote on Feb 3^rd, 2012, 6:19am:

YCY,

YCY wrote on Feb 2^nd, 2012, 5:47pm:

Note that typically reltol*i >> iabstol. Error limit is abs(i)*reltol + iabstol, where i is influenced by relref.

Quote:

Check the gate and bulk currents for capacitive coupling from node V_D to gate/bulk. You will find that they are not part of the drain current.

- B O E

Hi, B O E

Since I probe the drain terminal to get the current waveform,
I do not know how to check the current that flows from V_D to gate/bulk.
Could you please state more specifically on this?
Thanks a lot.

YCY

Title: Re: voltage leakage in VCO's switching capacitor
Post by boe on Feb 3^rd, 2012, 8:26am

YCY,
unless you have gate leakage in your transistor model, you can simply take the gate current.
The easiest way to get the bulk current is to use a 4-terminal transistor (if available).

- B O E

Title: Re: voltage leakage in VCO's switching capacitor
Post by YCY on Feb 3^rd, 2012, 4:45pm

boe wrote on Feb 3^rd, 2012, 8:26am:

YCY,
unless you have gate leakage in your transistor model, you can simply take the gate current.
The easiest way to get the bulk current is to use a 4-terminal transistor (if available).

- B O E

Hi B O E

The MOS device I used is a 4-terminal transistor.
I probed the gate current and found it is exactly equal to the drain current but has opposite sign.
Does this mean the current flowing out of the Minus terminal of the Cap (I(/C2/Minus)) all goes to the gate terminal?
Besides, the source and bulk currents are all negligibly small.
So, it still confuses me why I(/C2/Minus~19uA) is not equal to I(M1/D~6uA), where goes the remaining 13uA (I(M1/S) & I(M1/B)<<1pA, )?

Thanks
YCY

Title: Re: voltage leakage in VCO's switching capacitor
Post by nrk1 on Feb 4^th, 2012, 6:02am

YCY,

Is the nMOS bulk connected to source or 0V? If the latter, there will be a reverse biased diode between drain/source and bulk which can discharge VD towards the bulk voltage, 0V.

Title: Re: voltage leakage in VCO's switching capacitor
Post by loose-electron on Feb 4^th, 2012, 7:42am

YCY wrote on Feb 2^nd, 2012, 6:35pm:

It obviously violates KCL, does anyone know why?

Thanks,
YCY

You need to take a close look at the
tolerance and error settings in your simulator setup.

My earlier comment about real world capacitors
having plate to plate leakage is still valid, but the
problem you showing here is probably simulator
error tolerance settings and their setup.

Title: Re: voltage leakage in VCO's switching capacitor
Post by YCY on Feb 5^th, 2012, 9:35pm

nrk1 wrote on Feb 4^th, 2012, 6:02am:

YCY,

Is the nMOS bulk connected to source or 0V? If the latter, there will be a reverse biased diode between drain/source and bulk which can discharge VD towards the bulk voltage, 0V.

Hi, nrk1

Yes the bulk is connected to 0V.
But the bulk current is near 0A, thus I guess it not the main cause.

Title: Re: voltage leakage in VCO's switching capacitor
Post by YCY on Feb 5^th, 2012, 9:46pm

loose-electron wrote on Feb 4^th, 2012, 7:42am:

Hi loose-electron

I agree with you. There must be something wrong in simulator setup.
However I cannot find where.

I tried several different settings, such as tightening reltol from 1e-3~1e-7 and iabstol from 1e-12~1e-15,
yet the currents from cap and into NMOS are still not equal.
I have also tried tightening gmin, which affects the discharging time of V_D.
Smaller gmin leads to longer time.
Nevertheless, the cap current and NMOS drain current are still not the same.

Do you have any suggestion about the accuracy settings that I can try to verify the circuit?

Thanks a lot
YCY

Title: Re: voltage leakage in VCO's switching capacitor
Post by boe on Feb 6^th, 2012, 1:05am

YCY,

YCY wrote on Feb 3^rd, 2012, 4:45pm:

...
I probed the gate current and found it is exactly equal to the drain current but has opposite sign.
Does this mean the current flowing out of the Minus terminal of the Cap (I(/C2/Minus)) all goes to the gate terminal?

Yes, it does.

Quote:

Hi loose-electron

I agree with you. There must be something wrong in simulator setup.
However I cannot find where.

What are your settings for gmin and cmin? Are they negligible compared to the impedances of your circuit elemens?
- B O E

Title: Re: voltage leakage in VCO's switching capacitor
Post by YCY on Feb 6^th, 2012, 6:12pm

boe wrote on Feb 6^th, 2012, 1:05am:

YCY,

YCY wrote on Feb 3^rd, 2012, 4:45pm:

Yes, it does.

Quote:

Hi loose-electron

I agree with you. There must be something wrong in simulator setup.
However I cannot find where.

What are your settings for gmin and cmin? Are they negligible compared to the impedances of your circuit elemens?
- B O E

Hi, B O E

I set gmin from 1e-12 to 1e-15, and it does affects the results.
The smaller the gmin, the longer the discharging time.
As for cmin, it seems to have no influence on the simulation results.
I tried to set cmin to 0, 0.1f, and 1f.

BTW, now I think nrk1 is right.
The reverse-biased diode between drain/bulk is the main cause that discharges VD to 0V.
Because if I connect bulk to 1.2V, VD will be charged to 1.2V rather than 0V.

But I still do not know why the current flowing out of the cap is not equal to that flowing into the NMOS.

Thanks,
YCY

Title: Re: voltage leakage in VCO's switching capacitor
Post by nrk1 on Feb 6^th, 2012, 6:28pm

Hi,

Strange. Not sure if D/S/B terminal currents which are probed include currents in the drain/source diodes. Some experiments to check:
1. Increase AD/PD of the MOS and see if the rate or droop increases.
2. Connect an identical MOS transistor with drain and source to the present circuit's drain, and gate to the present circuit's gate. Check if the rate of droop increases(because of extra diodes).

YCY wrote on Feb 5^th, 2012, 9:35pm:

nrk1 wrote on Feb 4^th, 2012, 6:02am:

YCY,

Is the nMOS bulk connected to source or 0V? ...

Hi, nrk1

Yes the bulk is connected to 0V.
But the bulk current is near 0A, thus I guess it not the main cause.

Title: Re: voltage leakage in VCO's switching capacitor
Post by YCY on Feb 6^th, 2012, 7:31pm

nrk1 wrote on Feb 6^th, 2012, 6:28pm:

nrk1 wrote on Feb 4^th, 2012, 6:02am:

YCY,

Is the nMOS bulk connected to source or 0V? ...

Hi, nrk1

Yes the bulk is connected to 0V.
But the bulk current is near 0A, thus I guess it not the main cause.

Hi nrk1,

I think your previous post (#11) is right, the reverse-biased diode between D/B results in the leakage of VD.
Because if I connect bulk to 1.2V, VD will be charged to 1.2V rather than 0V.
Thanks for your suggestion.

YCY

Title: Re: voltage leakage in VCO's switching capacitor
Post by boe on Feb 7^th, 2012, 10:15am

YCY wrote on Feb 6^th, 2012, 7:31pm:

...
Hi nrk1,

I think your previous post (#11) is right, the reverse-biased diode between D/B results in the leakage of VD.
Because if I connect bulk to 1.2V, VD will be charged to 1.2V rather than 0V.
Thanks for your suggestion.

YCY

If you connect the bulk of the nMOS to 1.2V, you will forward-bias the drain-bulk diode if V_D < 1.2V.
- B O E