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Design >> RF Design >> LNA's main transistor bias
https://designers-guide.org/forum/YaBB.pl?num=1328447490

Message started by currant on Feb 5^th, 2012, 5:11am

Title: LNA's main transistor bias
Post by currant on Feb 5^th, 2012, 5:11am

Hi,
I am designing LNA and to achieve NF less than 2dB@1GHz at current about 5mA, I need to increase width of main 1.8V transistor and decrease its Vgs. So, now I have Vgs less about 30 mV than NMOS VTH. Of course, I paid for that mode by IIP3, but I am worry about correct noise modelling of BSIM4.5 in this operation mode.
I've read that PSP model is correctly model noise in any transistor mode of operation, but what about BSIM4.5?

Many thanks.