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Design Languages >> Verilog-AMS >> Code level for analog block
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Message started by fabian on Feb 6th, 2012, 2:04am

Title: Code level for analog block
Post by fabian on Feb 6th, 2012, 2:04am

Dear All,

I am wondering if there is a standard for code level to model an analog block in veriloga. For example, code 0 could be the model in veriloga of only the pinout of the block, code 1 could be current supply of the block added from code 0 and so on ...

Best regards,
Fabian

Title: Re: Code level for analog block
Post by ywguo on Feb 9th, 2012, 1:04am

Hi Fabian,

Have you read any verilog-A manual, tutorial, books? I don't understand what you mean.

Yawei

Title: Re: Code level for analog block
Post by Geoffrey_Coram on Feb 13th, 2012, 10:44am

I've never seen that sort of thing done.  Would you specify it as a parameter to the model, or would you specify the modeling level at the design level?

I know the Verilog-AMS "paramset" concept allows for you to specify that a certain set of model parameters is "digital" and another is "analog" so that you could have the simulator pick the appropriate model card for speed or accuracy, depending on the context.  But I've never seen anyone actually do it.

Title: Re: Code level for analog block
Post by fabian on May 11th, 2012, 2:32am

It has nothing to do with a parameter to be implemented in veriloga. I mean if there is a standard to define code level for analog block such as for exemple:
  only terminal declaration on a code makes code level 0
  having current consumption on top of level 0 makes code level 1
  and so forth ....

The answer could be there is no standard and it is down to each individual company strategy. I am interesting to start from somewhere.

Best regards,
Fabian

Title: Re: Code level for analog block
Post by carlgrace on Jul 11th, 2012, 6:17pm


fabian wrote on May 11th, 2012, 2:32am:
It has nothing to do with a parameter to be implemented in veriloga. I mean if there is a standard to define code level for analog block such as for exemple:
  only terminal declaration on a code makes code level 0
  having current consumption on top of level 0 makes code level 1
  and so forth ....

The answer could be there is no standard and it is down to each individual company strategy. I am interesting to start from somewhere.

Best regards,
Fabian


I developed Verilog-A and Verilog-AMS models for three different organizations and I have never seen anything like it.  Most people pretty much follow the style in Ken's book (you can see it in the example code on this website)

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