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Design >> Analog Design >> capless LDO line regulation problem
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Message started by sri.sagar on Feb 9^th, 2012, 10:16pm

Title: capless LDO line regulation problem
Post by sri.sagar on Feb 9^th, 2012, 10:16pm

Hi everyone,
I have implemanted robert millikens capless LDO in 90nm technology,which has 3.3V input and 2.8V output for a load of 100pf(internal) with max load current of 50mA. I am getting line regulation of 31mV/V at 50mA(max) and 11mV/V at 0mA(min) and psrr is -35dB at 100Khz, accourding to my knowledge it is bad. how can i improve my line regulation and psrr. and all other parameters are turning out to be good ,say my open loop gain is 61.2dB ,load regulation is 0.33 V/A,settling time is 2us.

And i also want to improve my deltavout which is 16mv(presently)

Please help me.
thanks

Title: Re: capless LDO line regulation problem
Post by lunren on Feb 10^th, 2012, 3:08pm

It was your design results or your measurement results?

Since you said the loop gain is good, better check if your reference generate has good line regulation.

PSR maybe is not that bad. Depends on your application. Trying to push your dominant pole to higher frequency to see if PSR @ 100K get improved or not.