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Design >> Analog Design >> Low noise design help
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Message started by raja.cedt on Feb 12^th, 2012, 2:39am

Title: Low noise design help
Post by raja.cedt on Feb 12^th, 2012, 2:39am

hello all,
i have some doubts regarding noise of an normal Band gap. I am assuming that normal text book band gap and R1 is the one which generates PTAT current and R2 is the resister which generates PTAT voltage and N is the bjt area ratio.

Noise from the op amp and top pmos current sources noise will be scaled by (R2/R1)^2. Based on PTAT and CTAT slope r2/r1*ln(N) will be decided, so now my Question is many people use bjt ratio N as 8 (for symmetry purpose), why can't we increase this bjt ratio to 15, hence lesser r2/r1 will okay for cancellation and this reduction of r2/r1 will reduce the noise impact.

Thanks,
raj.

Title: Re: Low noise design help
Post by RobG on Feb 12^th, 2012, 4:15pm

Raj - the main reason people use the 8:1 ratio is that the person before them used an 8:1 ratio ;D

A bigger ratio will help noise. In fact it will help just about everything. You can also get a bigger ratio by scaling the currents in addition to the area. Also, at some point the current density in the "big" bipolar becomes low enough that it starts to behave non-ideally. But up to that point, bigger ratio is better...

A more efficient way to accomplish this is to put the bipolars in series to generate the PTAT voltage. If you put two 8:1 diodes in series the voltage would be 2*Ut*ln(8) which is the same as if you had used a 64:1 ratio. The bandgap in fig 3 of my paper <click here> uses Darlington connected devices to get the increased PTAT voltage.

Title: Re: Low noise design help
Post by raja.cedt on Feb 13^th, 2012, 2:50am

hello Robg,
seems you are an expert in BGR so i will ask some Questions, even if you are busy please don't mind answer after some time.

1.Regarding noise, i got your point. It can be minimized by reducing ratio. About temp stability i need 50ppm, so i would like to know with normal BGR what is the typical ppm and if i want 50PPM what are techniques should i use.
2.About the op amp what is the main criterion to design, when i designed i just used simple op amp. Is there basic idea on Bandwidth and gain of the op amp. I know it has to be low Offset, because it will be directly coming at the o/p.

your paper was nice !!!!!!!!!.

Thanks,
Raj.

Title: Re: Low noise design help
Post by RobG on Feb 13^th, 2012, 3:11am

raja.cedt wrote on Feb 13^th, 2012, 2:50am:

Thanks for the compliments.

ppm will depend on your temperature range. You can expect about 4mV drop from 30C to 125C (or from 30C to -55C) in a perfectly tuned bandgap, plus whatever PTAT error you get from mismatches and process corners.

Quote:

2.About the op amp what is the main criterion to design, when i designed i just used simple op amp. Is there basic idea on Bandwidth and gain of the op amp. I know it has to be low Offset, because it will be directly coming at the o/p.

I'd say the biggest mistake people make is underestimating the requirements of the opamp. Your opamp will be configured in a gain of 8 or so, so all of your parameters that depend on loop gain will reduced by 18 dB. Power supply rejection, load rejection, and systematic offset are probably the ones that will hurt the most. And for the same reason, your offset and noise will be gained up by that factor of 8. (Using a high ratio of current densities like we talked about will reduce the amount of gain needed, which is why it is so important.)

There are two schools of thought on bandwidth - way lower than the load bandwidth so the output won't move with transient loads, or way higher so that it will settle quickly. To get a low bandwidth you'll need a huge compensation capacitance, or you'll have to lower your loop gain which will reduce your PSRR, load rejection, etc. I can't think of a case where I've opted for the "low bandwidth" solution unless I had an external capacitance.

Good luck!
Rob

Title: Re: Low noise design help
Post by raja.cedt on Feb 15^th, 2012, 2:20am

hello robg,
may be last Question in this post. Some how i didn't understand the above explanation for op amp, i know op amp noise and offset will be reflected directly at the o/p with some multiplication, but how gain will impact, may be if i increase the gain it may impact noise. One more question is are you ware of any calibration techniques to get better temp ppm?

Thanks a lot for spending some time fore this and it helped really a lot for me.
Thanks,
Raj.

Title: Re: Low noise design help
Post by RobG on Feb 15^th, 2012, 7:08am

raja.cedt wrote on Feb 15^th, 2012, 2:20am:

I was talking about loop gain. For example, if your opamp loop gain is 80 dB, when you use it in a bandgap where the delta-vbe term is gained up by a factor of 8 (18 dB), then the loop gain will be 62 dB.

Quote:

One more question is are you ware of any calibration techniques to get better temp ppm?

You can trim it if that is what you mean. It is easier to explain with a schematic, but if the offset of the opamp is zero then the bandgap can be trimmed to the same voltage at room temperature to achieve about 0 ppm. It is a good exercise to show that all the mismatches and corners (except offset) result in a PTAT error and can be trimmed out by adding a PTAT term. Trimming can be done by changing the resistor ratio or the current in one of the bipolars. You can't just put an adjustable voltage divider on the output because that won't add a PTAT term.

CMOS opamp offset is not PTAT so it can make it difficult to get 0 ppm at room if it is large.

You can also add curvature compensation circuitry, but I'm not sure that you can do a single temperature trim to get 0 ppm. (The technique I've been using allows this, but it is patented.)

There might be a tutorial out there that explains this better than I can. Maybe Rincon-Mora?

Best,
Rob Gregoire

Title: Re: Low noise design help
Post by mists on Feb 20^th, 2012, 7:51am

RobG, one simple question, you say "if the offset of the opamp is zero then the bandgap can be trimmed to the same voltage at single room temperature to achieve about 0 ppm", but as the BJT's ideal voltage is not known, and it will change in different process. even for same process, it change in different corner, then how to trim the Bandgap to 0 ppm at single room temperature? how to get the target bandgap output voltage that should I trim at room temperature to get 0 ppm? thanks!

Title: Re: Low noise design help
Post by RobG on Feb 20^th, 2012, 10:19am

mists wrote on Feb 20^th, 2012, 7:51am:

First you figure out what the voltage is at the output that gives you zero TC. Usually you have to do this with actual measurements. It will be about 1.23 V. This is often called the "magic voltage" because no matter what your bipolar or resistor corner is, or even what yout bipolar or resistor mismatch is, you can trim the bandgap to this point and it will bring it back to 0 TC. Note that your trim circuit must add/subbtract a PTAT voltage to accomplish this. This can be done by trimming the resistor ratio.

Google "Bandgap Magic Voltage" for more information on this.

Title: Re: Low noise design help
Post by mists on Feb 21^st, 2012, 3:51am

then you mean first I should measure some sample at different temperature, then get the bandgap magic voltage at room temperature for 0 ppm, so other sample can trim to the magic voltage at room temperature to get 0 ppm?

Title: Re: Low noise design help
Post by RobG on Feb 21^st, 2012, 6:15am

mists wrote on Feb 21^st, 2012, 3:51am:

yes