The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> VHDL and Verilog AMS Co-Simulation
https://designers-guide.org/forum/YaBB.pl?num=1329500397

Message started by despap on Feb 17^th, 2012, 9:39am

Title: VHDL and Verilog AMS Co-Simulation
Post by despap on Feb 17^th, 2012, 9:39am

Hi all,,
Is it possible to simulate VHDL,Verilog-A and Spectre together for AMS flow.
I have a VHDL code for a block and Verilog-A behavioral model for an analog block and one more transistor level block.
I checking any flows to simulate these three together.

Any ideas/help folks..!!

Thanks.!

Title: Re: VHDL and Verilog AMS Co-Simulation
Post by boe on Feb 23^rd, 2012, 3:38am

despap,

Yes, that is possible.

- B O E