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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> gm over Id method for low power opamp for bandgap https://designers-guide.org/forum/YaBB.pl?num=1329508181 Message started by mixed_signal on Feb 17th, 2012, 11:49am |
Title: gm over Id method for low power opamp for bandgap Post by mixed_signal on Feb 17th, 2012, 11:49am Hi, I am going to design an opamp for band gap refernce circuit. I want to keep it in weak inversion and use gm over id. 1. I want my op amp (2 stage Miller OTA) gain to be high and low offset. Shall i consider the bandwidth of the opamp for PSRR. 2. In weak inversion gain is dictated by lambda or channel length. How should i choose W, gm and current. i want the opamp to dissipate as low current as possible. 3. In weak inversion gm/Id is constant. So i would like to bias it in the knee of gm/id vs normalised current since going much into subthreshold wont be helpful as it would increase device sizes. Once i select gm/I and normalised then how do I choose W? Thanx |
Title: Re: gm over Id method for low power opamp for bandgap Post by Dan Clement on Feb 17th, 2012, 8:03pm Why do you want to bias into weak inversion? What will your BGR be used for? Your DC PSRR will be pretty high but you will have a very low bandwidth if basing deep into sub threshold (assuming you are intending to use low currents). Typical transistor models will not model us threshold well... Can you take some risk and do a test chip? |
Title: Re: gm over Id method for low power opamp for bandgap Post by mixed_signal on Feb 19th, 2012, 8:12am Hi Dan, BGR will be used as refrence in temperature sensor for RFID applications which requires for low power consumption. So, i want to keep it in weak inversion. I want low offest in the opamp and so weak inversion. I think u have greater current mismatch but less offset in weak inversion. What type of opamp is best suited for BGR? Is it two stage MIller with grounded capacitor? Can u suggest me an opamp where Vdd noise directly appears at the output? This ensures Vgs of the PMOS will be Vdd noise resitant since both gate and source will have correlated noise.. in a typical BGR I am taping out multiple experimental chips. I can take the risk!!!! Thanks |
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