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Modeling >> Behavioral Models >> asking about the implicit equation when using verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1329781260

Message started by dabier on Feb 20^th, 2012, 3:40pm

Title: asking about the implicit equation when using verilog-A
Post by dabier on Feb 20^th, 2012, 3:40pm

I was doing a behavior modeling of electronics devices. and in the model i need to declare a real type variable. and this variable is a function of time and can be defined from a differential equation implicitly, so can i just put the equation in the model and will the simulator automatically handle this? i just know that only a contribution can handle this implicit equation, how about a variable? thanks!!

Title: Re: asking about the implicit equation when using verilog-A
Post by Geoffrey_Coram on Feb 21^st, 2012, 6:13am

I'm pretty sure you'll need to set up a contribution to handle this; this will force you to select a discipline for the variable, which then sets the tolerances (absolute and relative) so that the solver knows how accurately it needs to resolve the value.

Title: Re: asking about the implicit equation when using verilog-A
Post by dabier on Feb 21^st, 2012, 9:04am

Thank you very much. i know what to do now!!

Title: Re: asking about the implicit equation when using verilog-A
Post by boe on Feb 23^rd, 2012, 3:36am

dabier,

you might want to try an indirect branch assignment:

Code:

V(out) : V(in) == 0 ; //find V(out) such that V(in) is zero

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