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Design >> Mixed-Signal Design >> problem with small capacitor in layout
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Message started by nus_lin on Feb 23^rd, 2012, 8:47pm

Title: problem with small capacitor in layout
Post by nus_lin on Feb 23^rd, 2012, 8:47pm

dear guys,

i have a similar problem in using a small capacitor in layout. The minimum MOM capacitor offered by the design kit is around 15ˣ15um2,which is much larger than what we want. Therefore, if my unit capacitor is smaller than that value, I am not able to pass the LVS check, and can not run the post-layout simulation either.

can anyone advise me how to get this done?

thank you in advance.

regards,
HE LIN

Title: Re: problem with small capacitor in layout
Post by yvkrishna on Feb 23^rd, 2012, 11:44pm

hi HE LIN,

I understand that the minimum cap value realizable as per layout guidelines is higher that what you need in the design.

What is the order of cap value you are looking for ? if it too small the adjacent parasitic cap can simply dominate it.

And you can use caps in series , or a combination of series and parallel caps to get to the value you wanted.

Regards,
yvkrishna

Title: Re: problem with small capacitor in layout
Post by raja.cedt on Feb 24^th, 2012, 2:30am

Why don't you make MIM caps by yourself in top metal?? It offers less capacitance based on your requirements. people go for MOM cap only if they need big capacitors but in your case it is different. If you want to go with PDk caps as vamsi suggested go with series combinations of big capacitors, in fact this is a good option if you need less mismatch as well..

Enjoy

Title: Re: problem with small capacitor in layout
Post by loose-electron on Feb 24^th, 2012, 2:13pm

what value of C are you looking for?
what is the value of parasitic C presented to substrate by the metal interconnect
at the node of interest?

if those two values are anywhere near each other you need to redesign your circuit to use a larger C.

Title: Re: problem with small capacitor in layout
Post by nus_lin on Feb 24^th, 2012, 7:11pm

thank you, vamshikrishna, raja.cedt, and loose-electron

actually i am already using c-2c architecture to reduce the effective capacitance.

the process i am using is 65nm, where mim cap is impossible. the only choice is mom cap. the unit capacitor i am trying to implement is 8fF, which should be much less than parasitics.

the ninimum mom cap in design kit uses 25 fingers, and is 32fF. so i am quite sure, if there is a way to adjust the minimum finger requirement so that i can use 9fingers, then things will become quite easy.

problem is how?

yvkrishna wrote on Feb 23^rd, 2012, 11:44pm:

Title: Re: problem with small capacitor in layout
Post by RobG on Feb 25^th, 2012, 8:50am

You can build a cap with nine fingers if you like, but you will have to waive the DRC rule violation which is a matter of company policy, not physics (bear in mind the 9 finger cap isn't going to be as accurate as the 25 fF cap - watch parasitics). You need to be talking with your supervisor and process guys about this to see if they will let you build a cap that small since it will violate the rules.

At ISSCC this year someone had a 0.6 fF cap in their design.

nus_lin wrote on Feb 24^th, 2012, 7:11pm:

Title: Re: problem with small capacitor in layout
Post by loose-electron on Feb 25^th, 2012, 12:46pm

"At ISSCC this year someone had a 0.6 fF cap in their design."

Yeah, and I have seen a lot of other stupid stuff in papers and presentations.

Things like that get lost in the process variance, or got added to tweak
a simulation, and don't have a lot to do with what happens on silicon.

I remember a S&H circuit where it was really small hold
capacitor, and when I asked the designer about the input capacitance
of the transistor connected to it, they drew a blank.

Turns out the input capacitiance of the next transistor was
about 50X bigger than the "hold" capacitor.

Title: Re: problem with small capacitor in layout
Post by loose-electron on Feb 25^th, 2012, 12:49pm

nus_lin wrote on Feb 24^th, 2012, 7:11pm:

i am trying to implement is 8fF, which should be much less than parasitics.

a controlling capacitor in a circuit should be much larger than the parasitics
at the node. Not smaller.

You want your explicitly defined device to be the primary control
not the parasitics.

Title: Re: problem with small capacitor in layout
Post by nus_lin on Feb 27^th, 2012, 1:06am

sorry, by less i actually mean bigger.

loose-electron wrote on Feb 25^th, 2012, 12:49pm:

nus_lin wrote on Feb 24^th, 2012, 7:11pm:

i am trying to implement is 8fF, which should be much less than parasitics.

a controlling capacitor in a circuit should be much larger than the parasitics
at the node. Not smaller.

You want your explicitly defined device to be the primary control
not the parasitics.

Title: Re: problem with small capacitor in layout
Post by Lex on Feb 27^th, 2012, 4:39am

You could try widening the spacings of the MOM and then verify the capacitance with the extraction tool. Since at that point you are making your own device, you are then dependent on the accuracy of your parasitic extractor (not without risk).

Title: Re: problem with small capacitor in layout
Post by RobG on Feb 27^th, 2012, 5:56am

loose-electron wrote on Feb 25^th, 2012, 12:46pm:

It was in a cap DAC for a SAR. Caps in the few fF range are becoming more common.

Title: Re: problem with small capacitor in layout
Post by boe on Feb 27^th, 2012, 7:04am

Hi,

RobG wrote on Feb 27^th, 2012, 5:56am:

loose-electron wrote on Feb 25^th, 2012, 12:46pm:

It was in a cap DAC for a SAR. Caps in the few fF range are becoming more common.

My tuppence worth: As long as you know what you are doing, fine. Otherwise, a recipe for disaster.
- B O E

Title: Re: problem with small capacitor in layout
Post by loose-electron on Feb 27^th, 2012, 2:24pm

RobG wrote on Feb 27^th, 2012, 5:56am:

loose-electron wrote on Feb 25^th, 2012, 12:46pm:

It was in a cap DAC for a SAR. Caps in the few fF range are becoming more common.

Yeah, and KT/C noise hasn't changed last I checked.

:)

Title: Re: problem with small capacitor in layout
Post by Lex on Feb 28^th, 2012, 3:58am

Hahahah =D

Good point!

Just out of curiosity, could you pass the link to that paper?

Title: Re: problem with small capacitor in layout
Post by RobG on Feb 28^th, 2012, 7:55am

Lex wrote on Feb 28^th, 2012, 3:58am:

Hahahah =D

Good point!

Just out of curiosity, could you pass the link to that paper?

Lex - the paper was 27.8 by Pieter Harpe, but you won't find much information there. However, last year he had a JSSC paper that talked about building a 0.5 fF capacitor with 90nm CMOS. It is here: http://ens.ewi.tudelft.nl/pubs/meijs11jssc.pdf

It seems to have some good information in it.

kT/C noise isn't much of an issue since the signal is sampled onto the entire DAC, not just the LSB cap.

rg

Title: Re: problem with small capacitor in layout
Post by loose-electron on Feb 28^th, 2012, 6:26pm

Fair enough Rob!

:)

Title: Re: problem with small capacitor in layout
Post by Lex on Mar 1^st, 2012, 2:21am

RobG wrote on Feb 28^th, 2012, 7:55am:

...

Lex - the paper was 27.8 by Pieter Harpe, but you won't find much information there. However, last year he had a JSSC paper that talked about building a 0.5 fF capacitor with 90nm CMOS. It is here: http://ens.ewi.tudelft.nl/pubs/meijs11jssc.pdf

It seems to have some good information in it.

kT/C noise isn't much of an issue since the signal is sampled onto the entire DAC, not just the LSB cap.

rg

Thanks for the paper Rob!

To me, what is striking is that they conclude that the systemic DNL is dominating, suggesting systematic layout issues for which they say that they are not detected by the extraction tool. No extra words are spent on this very important matter. So basically they have a fancy, self built, (EM?) extractor which does not correspond to the actual thing. That is not really assuring if you have to explain this to a customer.

Next, the fact that they have a total capacitance of 377fF of which 251fF is redundant, just shows this is another academic shot to score a paper at a conference. Which is of course legitimate, since funds depends on of accepted papers. But in essence it shows that you do not gain much by using such small capacitors.

Anyhow again thanks for the paper, but to me it advocates not to use such small capacitors.

Title: Re: problem with small capacitor in layout
Post by Vladislav D on Mar 1^st, 2012, 2:35am

Lex wrote on Mar 1^st, 2012, 2:21am:

RobG wrote on Feb 28^th, 2012, 7:55am:

Even with a proper extraction tool it is very hard to layout this capacitor array. You always have some error between MSB cap and LSB. Moreover you cannot include the package and wirebonds effects to the extractor.

Redundant parasitic capacitance decreases only the full-scale range. It does not degrade performance....

Title: Re: problem with small capacitor in layout
Post by RobG on Mar 1^st, 2012, 6:48am

Lex wrote on Mar 1^st, 2012, 2:21am:

To me, what is striking is that they conclude that the systemic DNL is dominating, suggesting systematic layout issues for which they say that they are not detected by the extraction tool. No extra words are spent on this very important matter. So basically they have a fancy, self built, (EM?) extractor which does not correspond to the actual thing. That is not really assuring if you have to explain this to a customer.

Next, the fact that they have a total capacitance of 377fF of which 251fF is redundant, just shows this is another academic shot to score a paper at a conference. Which is of course legitimate, since funds depends on of accepted papers. But in essence it shows that you do not gain much by using such small capacitors.

Anyhow again thanks for the paper, but to me it advocates not to use such small capacitors.

I haven't looked at it closely so I can't tell if it is practical or if I'm missing something. Not sure what you mean by redundant, or if it matters. The parasitics on the bottom side should have negligible effect since that side is switched. And parasitics on the top side only attenuate the signal provided to the comparator. This will cut into your SNR, but won't affect DAC linearity.

What do you think? I didn't see where any calibration was done but could have missed it.

rg

Title: Re: problem with small capacitor in layout
Post by Lex on Mar 2^nd, 2012, 4:57am

RobG wrote on Mar 1^st, 2012, 6:48am:

...
I haven't looked at it closely so I can't tell if it is practical or if I'm missing something. Not sure what you mean by redundant, or if it matters. The parasitics on the bottom side should have negligible effect since that side is switched. And parasitics on the top side only attenuate the signal provided to the comparator. This will cut into your SNR, but won't affect DAC linearity.

What do you think? I didn't see where any calibration was done but could have missed it.

rg

The way I see it, there are two things that makes the use impracticable.
i. The redundant capacitance reduces the power efficiency of ADC in such a way that you actually don't need such small capacitors in the first place. This part you refer to as 'negligible' effect.
ii. They don't have the adequate tools to model the capacitance. I don't think it is a matter of variance, as they call it themselves "systemic layout issues" that go undetected.

I didn't see any calibration either. What kind of calibration do you suggest for such a small capacitor array? Correct it digitally afterwards?

Title: Re: problem with small capacitor in layout
Post by RobG on Mar 2^nd, 2012, 6:57am

Lex wrote on Mar 2^nd, 2012, 4:57am:

You may be correct, but I didn't look closely enough at it to determine if what you say is true. Their power numbers are very low.

Quote:

ii. They don't have the adequate tools to model the capacitance. I don't think it is a matter of variance, as they call it themselves "systemic layout issues" that go undetected.

As we say, cowboy up! ;D You might recall that I don't have a lot of faith in models anyway, and I don't think designers should. I personally am ok with this sort of stuff if it is really needed as long as the limitations are known, but I "grew up" with much less sophisticated modeling. You have to take some rough estimates of the parasitics and also use designs that are insensitive to it. On the other hand, you wouldn't want to use these tiny capacitors if you can get the performance with a better modeled topology!

Quote:

I didn't see any calibration either. What kind of calibration do you suggest for such a small capacitor array? Correct it digitally afterwards?

My point was that calibration isn't needed in spite of the very small capacitance so they must be doing something correct.

I'm seeing so many papers with super low power numbers but they are using "calibration" to fix a design that is super sensitive to PVT. I'm not comfortable intentionally doing those types of designs even if I just wanted a paper, but (without looking to closely at it) this design seems like something I'd try if I really needed whatever the heck they needed. :)

Title: Re: problem with small capacitor in layout
Post by loose-electron on Mar 2^nd, 2012, 1:27pm

"grew up with less sophisticated modelling"

/(Insert grumpy old dude comment here)

Didn't have simulators "back in the day"

/* (End grumpy old dude statement)

Although that's true (my first couple of years as a chip
designer was board design morphed into a chip, or bipolar design
on paper getting dumped into silicon) I still don't trust most
semiconductor models. But, I don't tale the Bob Pease
attitude the "spice lies" either.

PVT and Matching variance is so ugly that I have been including
alignment, offset mismatch, and "adjustment knobs" in my designs
since about 0.35 micron and smaller. If its CMOS it is going to vary.

Title: Re: problem with small capacitor in layout
Post by Maks on Jun 21^st, 2012, 6:46pm

nus_lin wrote on Feb 23^rd, 2012, 8:47pm:

You can remove device instances for the unit caps from the netlist, and treat all capacitive components as parasitic - AND use a high-precision capacitance extraction tool based on a field solver.
this will give you a much more reliable capacitance results - both intended capacitance and parasitic coupling capacitance values - as SPICE models for the capacitors are not accurate at all for small capacitors that are exposed to the outside world (i.e. not properly shielded) and that have large parasitics.

Here is a couple of relevant links:

http://www.electronics-eetimes.com/en/faraday-selects-silicon-frontline-s-f3d-for-accurate-3d-extraction-of-adcs.html?cmp_id=7&news_id=222906109

http://www.edaboard.com/thread159589.html