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https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> SpectreVerilog: "reset" signal stays in "stx" https://designers-guide.org/forum/YaBB.pl?num=1330153539 Message started by ahhfyz on Feb 24th, 2012, 11:05pm |
Title: SpectreVerilog: "reset" signal stays in "stx" Post by ahhfyz on Feb 24th, 2012, 11:05pm Hi, everyone! I am simulating a mixed signal system using SpectreVerilog. In digital part, there is a "reset" pulse signal, whose width is 100ns. However, it stays in "stx", therefore the digital circuits cannot be reset, and simulation result is no sense. How could this happen? Thank you! |
Title: Re: SpectreVerilog: "reset" signal stays in "stx" Post by boe on Feb 27th, 2012, 6:37am Hi Ahhfyz, It is difficult to give you a concrete answer with so little information: Which tool version do you use? Where does the reset come from? What IEs do you use? Do you simulate power-up phase? Waveforms? - B O E |
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