The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Cross statements and simulation speed
https://designers-guide.org/forum/YaBB.pl?num=1330461552

Message started by Bob Atwell on Feb 28^th, 2012, 12:39pm

Title: Cross statements and simulation speed
Post by Bob Atwell on Feb 28^th, 2012, 12:39pm

OK I am confused. (Not an unusual condition.)
Based on what I thought I knew, Version 2 below shoud run slightly faster than Version 1 since the assignment statements occur within the cross statement. However this seems not to be true and in my test case it actually runs very slightly slower. Can someone explain?

Thanks, Bob.

Version 1:
@(cross(V(s) - 0.5))
;
if (V(s) < 0.5)
y1 = 0;
else
y1 = 1;
V(q1) <+ transition( y1, td, tt );

Version 2:
@(cross(V(s) - 0.5, +1))
y1 = 1;
@(cross(V(s) - 0.5, -1))
y1 = 0;
V(q1) <+ transition( y1, td, tt );

Title: Re: Cross statements and simulation speed
Post by Frank Wiedmann on Feb 29^th, 2012, 12:53am

I guess that version 2 does two separate tests for a cross event at every timestep whereas version 1 only does one test. The test for the cross event might take considerably longer than the if statement because values from two different points in time are involved. In version 1, why don't you trigger the if statement with the cross event?

Title: Re: Cross statements and simulation speed
Post by Bob Atwell on Feb 29^th, 2012, 5:42am

Thanks, that makes sense. The real model I was working on is a bit more complicated than this example but I think I can streamline it some.

Thanks again.