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Design >> Analog Design >> Opamp polaritiy
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Message started by raja.cedt on Mar 3^rd, 2012, 12:32pm

Title: Opamp polaritiy
Post by raja.cedt on Mar 3^rd, 2012, 12:32pm

hello all,
i am reading a patent on charge pump for low spur PLL, find the attached fig. but the basic problem is during M1,M2 turn on opamp has -ve feedback but how about feedback polarity when M5,M6 on.

Here i assume tail current source is realized by nmos whose gate is driven by opamp.

Thanks,
raj.

Title: Re: Opamp polaritiy
Post by Vladislav D on Mar 3^rd, 2012, 1:09pm

There are two feedback loops here: negative and positive. To make the circuit stable, loop gain of the positive loop should be smaller. This is achieved by the divider, formed by C1 and R1.

Looks like, at high frequency, the loopgain of the negative loop increases...

Title: Re: Opamp polaritiy
Post by raja.cedt on Mar 4^th, 2012, 12:56am

hello,
think about dc always, then ac.

Thanks,
Raj.

Title: Re: Opamp polaritiy
Post by loose-electron on Mar 4^th, 2012, 5:22pm

The op-amp does not see the high frequency switching.

Interesting configuration - You are changing
the charge pump current
to maintain common mode voltage.

Most of the time I have seen the opamp
maintain the voltage of the other side of the H-Bridge

Title: Re: Opamp polaritiy
Post by ywguo on Mar 17^th, 2012, 7:48am

Hi raj.

I don't know what's the purpose of that charge pump scheme. But I think One node, like Vx, probably is set to a common mode voltage. So you remove one loop.

Yawei

Title: Re: Opamp polaritiy
Post by AnilReddy on Mar 20^th, 2012, 12:25am

hi raja,

if M1 & M2 are turned on op-amp is in negative feedback configuration, if otherwise, the op-amp is in positive feedback configuration...

Thanks
Anil

Title: Re: Opamp polaritiy
Post by raja.cedt on Mar 20^th, 2012, 2:04am

hello anil,
whats the difference between my first post and your post?