The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Modeling >> Behavioral Models >> How to do random simulation on parameters defined in a verilog-A model?
https://designers-guide.org/forum/YaBB.pl?num=1331115016

Message started by manodipan on Mar 7^th, 2012, 2:10am

Title: How to do random simulation on parameters defined in a verilog-A model?
Post by manodipan on Mar 7^th, 2012, 2:10am

Hi All,
I want to random simulations on some parameters defined in my verilog-A model. Can you give some suggestions?

Title: Re: How to do random simulation on parameters defined in a verilog-A model?
Post by Geoffrey_Coram on Mar 7^th, 2012, 6:42am

I can't give any suggestions without a better idea of what you're trying to do.

Are you trying to do something with $random or $rdist in the Verilog-A model, or do you just want to pass some random values to parameters of your module (so you would just put the appropriate GAUSS calls in the netlist)?

Title: Re: How to do random simulation on parameters defined in a verilog-A model?
Post by manodipan on Mar 8^th, 2012, 9:11pm

Hi,
Passing on a list of parametrs is ok,but if i don't want to do then how to apply randomness to any parameter let's say random width variation and i want to know random distribution of the output current....

Title: Re: How to do random simulation on parameters defined in a verilog-A model?
Post by Geoffrey_Coram on Mar 9^th, 2012, 6:48am

Like I said: your two options are to pass GAUSS as a parameter value, or within the module to use one of the $rdist_ functions to add a variation to the width that's actually used in the current computation. Be careful, though, that you don't get a different random value for each timepoint if you use the latter approach.