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Message started by ssm on Mar 11th, 2012, 12:26am

Title: mixed language simulation
Post by ssm on Mar 11th, 2012, 12:26am

Hello,

I am wondering if possible to include my matlab adc and dac models, in spectre or spice simulations ?   Anyone similar like me, trying to avoid complicated data-converter simulations ?

SSM

Title: Re: mixed language simulation
Post by sheldon on Mar 11th, 2012, 6:02am

SSM,

  It might be easier just to write your own model for the data converter.
There are Verilog-A examples in ahdlLib and bmslib.

                                                                     Best Regards,

                                                                        Sheldon

Title: Re: mixed language simulation
Post by ssm on Mar 12th, 2012, 1:52pm

Sheldon, thanks for the kind reply:  

1). Do you mean just write a block in Verilog-A or similar language ?  

2). Is it possible to simulate matlab code together with netlist in Spice ?

SSM

Title: Re: mixed language simulation
Post by boe on Mar 13th, 2012, 1:14am


ssm wrote on Mar 12th, 2012, 1:52pm:
Sheldon, thanks for the kind reply:  

1). Do you mean just write a block in Verilog-A or similar language ?  
I think that is what Sheldon meant.

Quote:
2). Is it possible to simulate matlab code together with netlist in Spice ?
Co-simulation interfaces exist for some simulators. Which one do you use?

- B O E

Title: Re: mixed language simulation
Post by ssm on Mar 14th, 2012, 1:42pm

I actually use Cadence tools for analog/mixed-signal IC simulations.  (I might also use LTspice or Pspice for board level stuff).

Best,
ssm

Title: Re: mixed language simulation
Post by boe on Mar 15th, 2012, 1:52pm

ssm,
Search Mathworks home page for "Cadence cosimulation"...

- B O E

Title: Re: mixed language simulation
Post by ssm on Mar 15th, 2012, 2:14pm


Thanks BOE.  

ssm

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