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Message started by varun patial on Mar 14^th, 2012, 2:32am

Title: need help
Post by varun patial on Mar 14^th, 2012, 2:32am

i have designed single ended low noise amplifier with cascode source degeneration configuration to be operating at 2.14GHz and i m getting
S11 = -17.85dB
S21 = 12dB
both tuned at 2.15GHz
also input referred noise around 6.224E-18 V(sqr)/ Hz
but i m not able to design output impedance matching network so that S22 to be tuned at 2.14GHz
I tried pi matching network but that dropped my gain to 2dB
pls help
thanks in advance

Title: Re: need help
Post by loose-electron on Mar 14^th, 2012, 3:54pm

schematics and more information about the problem is needed

also, if you can rename your posting
to something more informative than "need help"

Title: Re: need help
Post by RFICDUDE on Mar 14^th, 2012, 7:37pm

As Jerry said, we need to see your topology before good suggestions can be provided.

If your gain is dropping because of matching then the problem is that you need to understand what to do to meet your gain requirement with matching. You need to find out what the output impedance is of your circuit and understand that matching will tune out the reactive part while loading the transistor with 1/2 the real part of the output impedance (conjugate match). The gain from your matched output to the load will be the square root of the impedance ratio sqrt(Rload/Rtransistor). If your load impedance is much lower than the output impedance of the transistor then the match will step down the voltage from the transistor to the load resistor. If the load is higher impedance than the transistor then the match will step up the voltage.

The gain with matching is something you can calculate and design for if you know what the output impedance of your amplifier is (before matching).

The other important point is topology and isolation to the input. If you have a common source (or emitter) amp without a cascode then the input and output networks are somewhat connected through the drain to source (or collector to base) capacitance. This output to input coupling makes it much more difficult to isolate the output and input matching circuits. However, if the circuit is a cascode structure for the input then there is high isolation between output and input making it a little easier to deal with matching and gain requirements for the design.

So tell us more about the topology.

Title: Re: need help
Post by varun patial on Mar 15^th, 2012, 11:13pm

thanks a lot ,
Sir I have attached the schematic of LNA and the sizes of mosfet are
W= 270u
L-0.18u
the LNA designed is based on power constrained noise optimization

Title: Re: need help
Post by varun patial on Mar 15^th, 2012, 11:23pm

thanks a lot RFICDUDE i need some explain how
The gain from matched output to the load is related to the square root of the impedance ratio sqrt(Rload/Rtransistor).

Title: Re: need help
Post by Vladislav D on Mar 16^th, 2012, 3:47am

varun patial wrote on Mar 15^th, 2012, 11:23pm:

thanks a lot RFICDUDE i need some explain how
The gain from matched output to the load is related to the square root of the impedance ratio sqrt(Rload/Rtransistor).

There is a mistake in the biasing....

Title: Re: need help
Post by Vladislav D on Mar 16^th, 2012, 3:50am

-If u need a narrow-band matching just put parallel RLC in the collector and remove that pi-crap from the output. With R u can vary the BW in expense of gain
-make C tunable to overcome process variation
-decouple the output port from the circuit

Title: Re: need help
Post by Vladislav D on Mar 16^th, 2012, 4:00am

In fact, if this is a standalone design, the pi-network will be formed by parasitics and u cannot do much about that.

Title: Re: need help
Post by loose-electron on Mar 16^th, 2012, 10:47am

Purpose of R1 & M2?

Why is there a signal generator on the output of the device?
(i think its a test tool, but please verify)

At first look, the DC op point does not seem to make sense,
could you please provide the node voltages and currents
at the DC operating point?

Title: Re: need help
Post by Vladislav D on Mar 16^th, 2012, 12:53pm

loose-electron wrote on Mar 16^th, 2012, 10:47am:

Purpose of R1 & M2?
(i think its a test tool, but please verify)

Jerry, I am just curious what you mean by a test tool?

Title: Re: need help
Post by loose-electron on Mar 16^th, 2012, 6:22pm

Set the voltage = 0 monitor the current in the voltage source.

It exists in the schematic,
but is meaningless in the final circuit on silicon.

Title: Re: need help
Post by varun patial on Mar 16^th, 2012, 11:03pm

thanks a lot all ,

At the output side Ireplaced pi network with simple L matching network and i got the gain around 13dB for the case when Vgs was equal to 0.934 volts and thresold voltage around 0.70 volts meaning by more current was flowing in main circuit and main problem with that was power was far above the nominal value. so i tried one of the solution:-
At the input side where R1 and M2 is used to provide dc operating point i modified the schematic replacing R1 by diode connected pmos as for low power requirement at the bias stage resistor requirement was of large resistor value around 10K with constraint on rf resistor i was getting maximum of 1.20K with single resistor so instead of connecting 9 resitors in series i tried two diode connected pmos and that work it and reduced my power significantly. also the Vgs at the input transistor become equal to 0.488 and threshold voltage around 0.477. But at the same time it reduced my gain from 13dB to 7dB.
I calculated small signal gain earlier it comes out to be ratio of load inductor to source degeneration inductor. but when i increase the value of load inductor it saturates the gain around 7dB while ohter parameters remains within nominal value(S11,S22,NF)pls suggest how to increase gain
Sorry i cant provide modified schematic because of weekend lab is closed. i will attach the schematic on monday.

Title: Re: need help
Post by RFICDUDE on Mar 17^th, 2012, 5:22pm

As Vladislav first pointed out, the gate bias circuit is not valid.

The input bias appears to be a current mirror reference diode, but the gate and drain are not tied together. The gate voltage of the input device appears to be indeterminate for the circuit shown.

Beyond the reference device issue, the current mirror reference device has a width=6u and the amplifier has width=0.24u resulting in a step down of 0.24/6=0.04 in current from the reference device to the amplifier. Typically we want a step up in current arising from the reference device width being smaller than the amplifier device it is biasing.

Title: Re: need help
Post by varun patial on Mar 18^th, 2012, 10:35pm

thanks a lot rficdude i rectify the problem regarding the biasing circuit also at the input side the sizes of driver and cascode mosfet is 370/0.18
but still gain is not increasing

Title: Re: need help
Post by varun patial on Mar 18^th, 2012, 10:36pm

schematinc with dc node voltages

Title: Re: need help
Post by Vladislav D on Mar 19^th, 2012, 1:50pm

First of all, please, draw a schematic clearly, if you want people help you. Electronics does not like rush.

Use the M parameter for transistors and inductors and make the connection between components reasonably short. Voltages in the schematic are hardly readable. Currents are important as well!

At this step of the design, I'd suggest to use ideal inductors, capacitors and the ideal current source to bias M2.

You must place a capacitor between the output port and the output of the amplifier in order to bias the transistors properly

Matching network at the input is too complex. It is possible to match input with a series inductor at the gate and some inductance at the source. You can do some research. The methodology to do this exist. For example, you can read http://www.amazon.com/Co-Design-Integrated-Receivers-International-Engineering/dp/1402031904

Title: Re: need help
Post by varun patial on Mar 21^st, 2012, 10:47pm

thanks a lot Vladislav D
i tried putting capacitance before the output port and that proved to be effective in decreasing my power . I have following query
1)how to decide where to use ideal passive components and where to use rf passive components in the schematic.
2) how to optimize the value of inductance i m attaching two files
i m confused how to set diameter,width and no. of turns.
for example with one file attached i can use single inductor of value 14.27nH
and with other one i can use two inductors of value around 7nH in series with varying values

Title: Re: need help
Post by varun patial on Mar 21^st, 2012, 10:48pm

2nf file

Title: Re: need help
Post by Vladislav D on Mar 22^nd, 2012, 4:39pm

Diameter, width, number of turns this is a physical design. At your design step this only distractions, as well as various non-ideal effects related to the physical implementation. I'd recommend to concentrate the efforts on electrical design. You can use 'ind' and 'cap' components from the analogLib and only specify an electrical values (uH, pF, etc.) .
Use ideal components everywhere, and when a circuit works replace them with the real ones.

varun patial wrote on Mar 21^st, 2012, 10:47pm:

i tried putting capacitance before the output port and that proved to be effective in decreasing my power .

what power do u mean?

Title: Re: need help
Post by RFICDUDE on Mar 22^nd, 2012, 5:23pm

I echo Vladislav's suggested, it is better to focus on the fundamentals of your design and then deal with implementation issues.

To answer your question about 1 inductor versus 2 in series, it is better from an area and loss perspective to use one physical inductor versus two in series to achieve a target inductance value. This is because the total inductance of the spiral inductor structure takes advantage of the mutual inductance between turns as part of the total inductance. When you break the inductor into two series inductors you loose some of the benefit of the mutual inductance because the two inductor are physically separated thereby reducing some of the mutual coupling between the turns in the separate spirals.

For the same inductance and similar Q, the area of a single spiral inductor will be less than two series spiral inductors.

Title: Re: need help
Post by varun patial on Mar 24^th, 2012, 5:29am

Thanks a lot Vladislav D and RFICDUDE,
i made use of pi network to tune my amplifier to 2.14GHz which was earlier tuned to 1.5GHz and i designed pi matching network by calculating the impedance graphically before C0(pls refer to schematic) it come out to be 100+j248 and matching this to 50 ohms but i think i m lacking somewhere in my approach. pls suggest that my approach is rite or wrong?

Title: Re: need help
Post by RFICDUDE on Mar 24^th, 2012, 11:43am

I am a little confused, 100+j248 ohms implies a series inductance of 18.36 nH at 2.15GHz.

Your first schematic (the only one with a C0) shows 1nH inductors in series with the gate and source (each), so I am not clear on why the input inductance appears to be so high.

Was the impedance 100-j248 at 2.15GHz?

Title: Re: need help
Post by varun patial on Mar 25^th, 2012, 12:40am

good morning everyone,
RFICDUDE i will answer to your question tommorrow
I am in big confusion
Vladislav D suggested to use ideal components from analoglib but as i have studied that at high frequencies passive components behaves differently as compare to ideal ones so if i use ideal components their behavior will remain same at high frequencies too.....so why not to use real components?
is those parameters e.g. diameter, no. of turns etc are important only while designing layout ?

Title: Re: need help
Post by RFICDUDE on Mar 25^th, 2012, 1:13pm

Yes, it is true that passive components you design/use are far from ideal, so it does make some sense to account for the differences early in the design.

But, when you are trying to design the circuit from first principles there are too many variables to balance if you are trying to account for all the non ideal parameters.

Right now you are having difficulties with the fundamental problem of matching the circuit and achieving a target or acceptable gain. It would be a validation of your design if you first calculated and simulated the performance with ideal components for the match (it is not going to perform any better than this with real components). As a second step, you would evaluate the impact of using real components (how much does the gain decrease from the ideal case).

Title: Re: need help
Post by varun patial on Mar 26^th, 2012, 2:36am

Thanx a lot @RFICDUDE,
as you were asking for the inductance of 18 nH at the input, I found that the current was lagging voltage. So I calculated Vp-p and from there I calculated time difference between both peak, and calculated mod zin .I am attaching the waveform i got

Title: Re: need help
Post by RFICDUDE on Mar 26^th, 2012, 4:20am

Estimating impedance from the time domain waveform is not the most reliable way to measure impedance.

I suggest using AC simulation to measure input impedance. Driving the input with an AC source you can measure the complex impedance as
z(f)=v(f)/i(f)
then break this down into real and imaginary components to determine what the input looks like at specific frequencies.

The other thing I noticed is that the input signal levels in your simulation are very large. Large enough to cause your amplifier to saturate. This might be part of your gain problem if you are also trying to measure gain with the same signal levels applied.

AC (or s-parameter) simulation will let you look at impedances and gain without overdriving the devices. Usually a designer will verify the linear design with AC (or s-parameter) analysis to make sure gain/matching are correct before moving on to transient or steady-state simulations to measure linearity and gain compression characteristics.

Title: Re: need help
Post by varun patial on Mar 29^th, 2012, 1:39am

with warm regards to all,(design using ideal LNA)
1) as per your point RFICDUCE regarding signal level i was taking it as
-60dBm because as i am designing LNA for WCDMA that has reception range of 2.11GHz to 2.17GHz by that BW of 60MHz.Noise floor was coming out to be
Noise floor (when no electronics noise added)= minimum dectable signal=kTB =-174dBm/Hz + 10log(60MHz)= -96dBm, for some window i was taking it as -60dBm, but still how much below or above can i take this value pls suggest
2) as per your suggestion RFICDUDE i calculated the input impedance by ac analysis but it doesnt give the satisfactory result it when calculated from the calculator comes out to be complex(27.838,72) and this value doesnt fit to design.i also tried s parameter analysis (Z11) it also gave same result i m attachig graphs suggest wether my approach is rite or wrong.
firstly sparameter results and then ac analysis result

Title: Re: need help
Post by varun patial on Mar 29^th, 2012, 1:41am

for v(f)/I(f) analysis

Title: Re: need help
Post by RFICDUDE on Mar 29^th, 2012, 4:32am

-60dBm is plenty small, so I am surprised that a -60dBm input signal is creating such large voltage and currents in the input circuit.

It looks like the S parameter and AC analysis results are in agreement (as best that I can tell). It is a good ideal to use the same frequency sweep range when comparing different analysis (AC and S-parameter) because it is difficult to visually look at two different ranges especially when one is linear and the other on a log scale.

At this point I need to ask which schematic are you simulating, and what components are included in the input circuit.
I had been assuming that you are using the original schematic you posted, but that you had removed the input pi network and now all measurements are directly into C0 in series with L2. But I am not sure that is the case because you show an AC current into C1.
So, please post your current simulation schematic to clarify exactly what we are looking at.

Are L1 and L2 fixed values of 1nH in your design (bond wire parasitic), or can you change them as part of your design?

Title: Re: need help
Post by varun patial on Mar 31^st, 2012, 6:36am

hello everyone,
hello RFICDUDE, sorry i forget to mention that with your suggestion i replaced the passive components (real) with the ideal ones (analoglib). I will attach the schematic shortly.
But before that i m confused , although it is stupid to ask this question but i didnt think over it earlier.
Its regarding the value of dc blocking capacitor.I was taking it earlier ar 10pF. But after doing some survey i found mixture of answer and now I am not able to find adequate value for dc blocking capacitor both at input and output. pls suggest how its value is choosen
1) I read it that it should be between 0 to 5 percent of input impedance but why so and if its true then for 50 ohms impedance at input impedance 5 percent of it gives 2.5 ohms of Xc so that give value of C (29pF) at working frequency(2.14GHz). but isnt it large value regarding to area constraint.
2) some relates its value from SFR of capacitor but i am not getting exact answer regarding value.