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Design >> Analog Design >> Capacitive voltage divider (Cadence Simulation)
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Message started by arupkg on Mar 15^th, 2012, 1:06am

Title: Capacitive voltage divider (Cadence Simulation)
Post by arupkg on Mar 15^th, 2012, 1:06am

What is the expected voltage when two equal capacitors in series are driven by a DC source(VD), and voltage is measured across one of the capacitors?

I thought the voltage across one capacitor should be half that of VD, but Cadence simulation shows it as zero. What is the reason. ?

Title: Re: Capacitive voltage divider (Cadence Simulation)
Post by buddypoor on Mar 15^th, 2012, 1:14am

I am a bit surprised about the Cadence result (0 volts) because - according to my experience - simulation programs require a dc path to ground for each node.
Thus, I would expect an error message.
Nevertheless, it's a task that cannot be solved by calculation (for ideal capacitors) - and in reality the voltage distribution is determined by the parasitic losses.

Title: Re: Capacitive voltage divider (Cadence Simulation)
Post by arupkg on Mar 15^th, 2012, 1:25am

Thanks very much buddy poor.

Yes, I got the warning from cadence saying "No DC path from net02 to ground". But by theory, the voltage should divide equally among the capacitances, right. That is how we say the equivalent capacitance is C/2 when two capacitances are connected in series, right?

Let us say the series capacitances are C1 and C2 and it is driven by two square waves (0-1.2V) 180 degree out of phase with each other at both ends of the series capacitors. How do we estimate the voltage at the mid-point? (This is a very typical MEMS half bridge)

Title: Re: Capacitive voltage divider (Cadence Simulation)
Post by buddypoor on Mar 15^th, 2012, 1:53am

arupkg wrote on Mar 15^th, 2012, 1:25am:

But by theory, the voltage should divide equally among the capacitances, right. That is how we say the equivalent capacitance is C/2 when two capacitances are connected in series, right?.......................

No, I don't think so.
As I have mentioned, the task cannot be solved for IDEAL capacitors connected to a dc source.
More than that, the calculation of the resulting capacitance if two such elements are in series is based on its capacitive impedances (reactances) which are defined for ac signals only.
_____________
I think, it's useful to explain my position:
* At first, IDEAL capacitors do not exist; thus, the question is of pure theoretical nature without any relation to reality. In reality, resistive lsses determine the voltage distribution.
* Secondly: We must not consider the steady-state condition. In contrary, what happens at t=0 (switch on of a dc voltage)? In a lossless circuitry there would be a current pulse of value infinite. Is this possible? Of course not. Thus, we again arrive at the resistive losses within the circuit.

Title: Re: Capacitive voltage divider (Cadence Simulation)
Post by raja.cedt on Mar 15^th, 2012, 5:15am

hello,
could you please tel me how your simulating, because simulator works for sure even with ideal capacitors, after all simulator model any non-ideal elements with ideal like adding some resistance in series with cap. I did small simulation and i gave 1 v and got .5v o/p.

Title: Re: Capacitive voltage divider (Cadence Simulation)
Post by Dan Clement on Mar 15^th, 2012, 6:00am

Spectre places a current source of value gmin on all floating nodes. This forces all floating nodes to zero for dc.

What you are simulating doesn't make sense as pointed out by previous replies.

Title: Re: Capacitive voltage divider (Cadence Simulation)
Post by HdrChopper on Mar 15^th, 2012, 8:38am

hi arupgk,

Are you running a DC op point or a TRAN analysis? Raja run a transient and he got what you should get, which is VD/2. But since it is a transient and there is a voltage step at t=0, then there will be current for charging the caps and you'll get the final voltage you are looking for.
.

Best
Tosei

Title: Re: Capacitive voltage divider (Cadence Simulation)
Post by RobG on Mar 15^th, 2012, 10:08am

Dan Clement wrote on Mar 15^th, 2012, 6:00am:

Spectre places a current source of value gmin on all floating nodes. This forces all floating nodes to zero for dc.

What you are simulating doesn't make sense as pointed out by previous replies.

I agree if you meant "conductance" not "current source."

Title: Re: Capacitive voltage divider (Cadence Simulation)
Post by loose-electron on Mar 15^th, 2012, 11:29am

arupkg wrote on Mar 15^th, 2012, 1:06am:

Simulation considerations aside (others seem to be covering the issue)
you generally do not want to use such a device in a design, unless there is some method to initialize, or hold the ratio.

Such as:

Resistors in parallel with the capacitors
Switch capacitor zero-out methods that get updated.

Free floating capacitors without defined DC parameters
tend to be rather unreliable in real world application.

Title: Re: Capacitive voltage divider (Cadence Simulation)
Post by arupkg on Mar 15^th, 2012, 7:08pm

Thanks raja.cedit, RobG, DanClement and HdrChopper for the replies. Appreciate it.

Actually I had run a transient analysis. There are two scenarios:
1. The series capacitive bridge is driven by a dc source: In this, the voltage at the midpoint shows zero.

raja.cedit, could you give some more info how you got the results you attached?

2. I used a Vpulse to drive the series capacitive bridge. In this case, the voltage jumps to 1V and dies out as a transient. This is explainable given that the node has a conductance = gmin connected to it.

Many thanks