The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Adding parasitic  information into verilog AMS https://designers-guide.org/forum/YaBB.pl?num=1331884696 Message started by zahrein on Mar 16th, 2012, 12:58am

Title: Adding parasitic  information into verilog AMS Post by zahrein on Mar 16th, 2012, 12:58am HI , How do we add SPEF(RC extraction) into verilog AMS?

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