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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Stack Memory verilog program- need help please https://designers-guide.org/forum/YaBB.pl?num=1332188005 Message started by sivashankarvela on Mar 19th, 2012, 1:13pm |
Title: Stack Memory verilog program- need help please Post by sivashankarvela on Mar 19th, 2012, 1:13pm Hi all, Following is my verilog program for stack memory. I am able write it in Stack but not able to read it from that. Please help me in this. //module module stack(clock,reset,remove,insert,data_in,data_out,error_read,error_write); input clock,reset,remove,insert,data_in; /*remove - the signal to enable the read operation data_in - variable to write the data into the stack insert - signal to enable the write operation data_out - variable to read from the stack error_read - This signal will be high when the stack is empty and the data is tried out to be read error_write - This signal will be high when the stack is full and the data is tried to be written*/ wire [7:0] data_in; output [7:0]data_out; output error_read,error_write; reg [1:0] cstate,nstate; reg error_read,error_write; reg [7:0] stack_reg [7:0]; reg [7:0] data_out; reg [2:0] write_buff; // for write operation /* parameter [1:0] idle=2'b00, write=2'b01, read=2'b10, error=2'b11; */ reg [2:0] read_pointer,write_pointer; reg [2:0] read_address,write_address,write_bufaddress; integer i; always@(posedge clock or negedge reset) begin if(!reset) begin for(i=0; i<8;i=i+1) begin stack_reg[i] <=8'h00; end write_pointer<=3'h0 ; read_pointer<=3'h0; write_buff <= 0; error_read <= 0; error_write <= 0; cstate <= 0; end else begin cstate <= nstate; write_buff <=write_pointer; //$display("state"); end end always@(remove or insert or cstate or data_in) begin nstate = 2'b00; error_read=0; error_write=0; write_pointer=0; data_out = 0; case(cstate) 2'b00: begin if((insert==1) && (write_buff !=7)) begin nstate = 2'b01; // $display("It is in idle state"); end else if((insert==1) && (write_buff==7)) begin nstate = 2'b11; end else if((remove==1) && (write_buff !=0)) begin nstate = 2'b10; end else if((remove) && (write_buff==0)) begin nstate = 2'b11; end else begin nstate = 0; end end 2'b01: begin stack_reg[write_buff] = data_in; write_pointer= write_buff+1; nstate=2'b00; end 2'b10: begin read_pointer = write_buff-1; data_out =stack_reg[read_pointer]; nstate=0; end 2'b11: begin if((insert) && (write_buff > 8)) begin error_write=1; end else if((remove) && (write_buff == 0)) begin error_read=1; end nstate=2'b00; end endcase end endmodule module test_stack; reg [7:0] data_in; reg reset,clock,insert,remove; wire error_read,error_write; //wire [7:0] stack_reg [7:0]; wire [7:0] data_out; stack in_stack(clock,reset,remove,insert,data_in,data_out,error_read,error_write); initial $vcdpluson; initial begin $monitor("reset=%b, data_in=%h, insert=%b,remove=%b, data_out=%h,error_read=%b,error_write=%b",reset,data_in,insert,remove,data_out,error_read,error_write); end initial begin clock=0; forever #5 clock=~clock; end initial begin #5 reset=1; insert=0; data_in=0;remove=0; #10 reset=0; insert=0;data_in=0;remove=0; #10 reset=1; insert=1;data_in=011;remove=0; #10 reset=1; insert=1;data_in=011;remove=0; #10 reset=1; insert=0;data_in=0;remove=1; #10 reset=1; insert=0;data_in=0;remove=1; #10 $finish;/* #10 reset=1; insert=1;data_in=2;remove=0; #10 reset=1; insert=0;data_in=0;remove=1; #10 reset=1; insert=1;data_in=3;remove=0; #10 reset=1; insert=0;remove=1; #10 reset=1; insert=0;remove=0; #1000 $finish;*/ end endmodule |
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