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Design >> Analog Design >> Reference buffer for ADC ??
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Message started by Ajay on Mar 24^th, 2012, 5:58am

Title: Reference buffer for ADC ??
Post by Ajay on Mar 24^th, 2012, 5:58am

I have a SAR ADC
clock period = 1/20Mhz
LSB size = Vref / 4096 for a 12 bit ADC
As a general rule the settling must be within (1/2)LSB in (1/2) clock period.

Is there any ADC reference buffer architecture that can fulfill such a tight requirement ? How much open loop gain do I need for the amplifier and how much is the bandwidth needed ? Thanks.

Title: Re: Reference buffer for ADC ??
Post by carlgrace on Apr 18^th, 2012, 5:30pm

You don't give enough information. For example, what is your reference voltage? That will tell us a lot. The clock isn't very fast, so really these specs probably aren't that bad.

You have two choices, you can make your reference really really slow (and low impedance) or you can make it so fast it settles in 1/2 clock period. The easiest thing to do, if you can spare the pads, is to bypass the heck out of the reference so it's peak transient is less than 1/2 LSB.

Title: Re: Reference buffer for ADC ??
Post by RobG on Apr 19^th, 2012, 9:20am

carlgrace wrote on Apr 18^th, 2012, 5:30pm:

If he makes it "slow" he'll have to watch out for signal dependent loading, which, if low frequency, will change the I*Rout drop of the buffer. Depending on the design, the drop could be more than 1/2 LSB.

I'm not sure open loop gain is all that important as it will only scale the reference slightly, which will result in a gain error. Often times people don't care about gain error. If they do, then your open-loop gain must be enough so that A/(1+A*β) < 1/2 LSB

Title: Re: Reference buffer for ADC ??
Post by Ajay on Apr 30^th, 2012, 1:36pm

My reference is 2.5V and I have a big capacitor of a few micro-farad connected to the reference buffer . This big cap acts as a voltage source for the DAC array. What architecture of opamp do I use to make the buffer ? I know I need a high gain and so a 2 stage opamp will be needed, but again the frequency compensation will be difficult. Thanks.

Title: Re: Reference buffer for ADC ??
Post by RobG on May 1^st, 2012, 4:24pm

Ajay, as you figured out it will be difficult to stabilize a two stage amplifier if it has a large load cap on the output. It is possible to use the load cap so set the dominant pole instead of the Miller cap, but you have to model bond wire inductance and series resistance. Look at how they do it with an LDO if you really want to go this route or maybe someone else can give more details.

An alternative structure that may meet your needs is a folded cascode opamp (ota) like:

That topology will be compensated by the load capacitor, yet still have high open loop gain. It is the "really really slow" option mentioned by Carl. It will act like a low pass filter with a pole at gm/(2*pi*Cload), where gm is the transconductance of the diff pair. The down side is that the output resistance of this circuit will be 1/gm so you have to make sure that the Iav/gm drop from the average current is less than the tolerance you require.

Title: Re: Reference buffer for ADC ??
Post by Ajay on May 2^nd, 2012, 1:08am

Hello Rob, Thanks for the message. The opamp is used as a unity gain buffer. There are no feedback resistors around it and hence the DC gain error will be 0. The output maybe offset from the input depending on the systematic and random offset of the opamp.
* If I had a resistive feedback N/W with a gain of say 2, then I would have to keep the gain very high in order to minimize the Gain error ( steady state o/p).
* But in my case its a unity feedback configuration and hence Vout = Vin and gain error = 0. I do not think I need a high gain to drive the capacitive DAC array (dynamic load). Maybe 60 dB should be enough.
However I will need a good bandwidth so as to meet the settling time specification.
Can you please give your opinion about this ?
Thanks in advance.

Title: Re: Reference buffer for ADC ??
Post by RobG on May 2^nd, 2012, 4:17am

Gain error due to finite opamp gain is related to "systematic" error. Instead of gain = 1, it will be A/(1+A). I think 60dB is fine.

Like Carl was saying earlier, you can do this two different ways. 1) a fast buffer that recovers before the end of the period, or 2) a slow buffer with a big filter capacitor that prevents the reference voltage from changing. With an external capacitor you are doing 2). You will never get an amplifier to be fast while loading it with a few uF.

That folded cascode amplifier will work fine in either approach assuming your SAR is switched capacitor so the amplifier doesn't have to drive a resistive load.