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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> negative feedback in latch comparator https://designers-guide.org/forum/YaBB.pl?num=1332846601 Message started by ellarguero on Mar 27th, 2012, 4:10am |
Title: negative feedback in latch comparator Post by ellarguero on Mar 27th, 2012, 4:10am hello i have a problem, i simulate a latch comparator with stb analysis the schematic is below i got a negative phase loop which means the feedback is negative, i can't figure out from where comes this negative feedback or is ir an artifact !!! now i removed the cross coupled pmos pair in the top like this and now the feedback is positive, i am really confused , please help me figuring out what's going on regards |
Title: Re: negative feedback in latch comparator Post by raja.cedt on Mar 27th, 2012, 5:05am hello, what is the intention of doing behind doing .STB for a latch or what is interested parameter from this simulator? Any how your Question is valid. What is the exact phase at at 1meg. Due to +ve feedback you +ve phase shift, but due to gds of the pmos and nmos you get _ve phase shift as well. So don expect pure +ve FB.for example if gds is grater than gm then there is -ve feedback rather +ve feedback. Thanks, Raj. |
Title: Re: negative feedback in latch comparator Post by ellarguero on Mar 27th, 2012, 6:32am hi Raj the intention is just to understand i believe the fb is always positive wether gds>gm or not, now if gm<gds the loop gain is not enough to induce latch i think there is an extra negative feedback du to the common source node (the drain of the current tail). i am trying to figure out how does it work |
Title: Re: negative feedback in latch comparator Post by raja.cedt on Mar 27th, 2012, 1:35pm hello, source node will be at ac ground, so how it will present -ve fb? |
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