The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> MOS aspect retio less than 1
https://designers-guide.org/forum/YaBB.pl?num=1333582616

Message started by mixed_signal on Apr 4^th, 2012, 4:36pm

Title: MOS aspect retio less than 1
Post by mixed_signal on Apr 4^th, 2012, 4:36pm

HI,

I am designing a 5T diff pair where I can use only 200nA for the current source. I want to keep the input diff pair in weak inversion for high gm and the loads and current source in strong inversion.

At such low current the aspect ratio of the transsitors in strong inversion is <1 approx. 1/5. Is it a problem?

I have 2 options:

1. Put all in weak inversion. Problem is current mirror mismatch and offset.

2. Put input pair in weak inversion. All others in strong inversion but with aspect ratio <1 approx. 1/5

Which is better?

What is the maximum L/W ratio without any issue?

Title: Re: MOS aspect retio less than 1
Post by Lex on Apr 5^th, 2012, 12:13am

You could check your foundry's documentation to see what lengths and widths are covered by the transistor models.
If you're going to work in the uA domain it is fairly normal to have l>w. I've been using up to 1/10 without any problems on several processes. Just make sure your width is a good amount larger than the minimum width of the transistor since you're using it for analog. A bit of trust in your PDK models is okay, but too much can be fatal ;)

Title: Re: MOS aspect retio less than 1
Post by mixed_signal on Apr 5^th, 2012, 5:57am

Thank you Lex!
I want a ratio of 1/20. My minimum width allowed is 160nm and length is 120nm. I am using width=500nm and length 10um. Is that OK for analog?

Thanks!

Title: Re: MOS aspect retio less than 1
Post by RobG on Apr 6^th, 2012, 6:08pm

mixed_signal wrote on Apr 5^th, 2012, 5:57am:

Thank you Lex!
I want a ratio of 1/20. My minimum width allowed is 160nm and length is 120nm. I am using width=500nm and length 10um. Is that OK for analog?

Thanks!

W=0.5um is fine. I'm using W=1um, L=40um for a similar amp right now. You might have to go longer than 10um to get the 1/f noise down.

I would expect (but do not know) that dummy devices are especially important for such narrow widths.

Title: Re: MOS aspect retio less than 1
Post by mixed_signal on Apr 6^th, 2012, 8:12pm

Hi RobG,

Thank you for your relpy!

I want to find the integrated noise at the Vref of my temperature sensor. What should be my frequency range over I should integrate? My sensor will be followed by sigma delta. The sensor should give 1 reading per minute.

I integrated from 1/60 Hz till flicker corner =10KHz and it was 6 uV.

Thanks!

Title: Re: MOS aspect retio less than 1
Post by Vladislav D on Apr 8^th, 2012, 3:34am

mixed_signal wrote on Apr 6^th, 2012, 8:12pm:

Hi RobG,

Thank you for your relpy!

I want to find the integrated noise at the Vref of my temperature sensor. What should be my frequency range over I should integrate? My sensor will be followed by sigma delta. The sensor should give 1 reading per minute.
I integrated from 1/60 Hz till flicker corner =10KHz and it was 6 uV.
Thanks!

Set the expected load and integrate the noise to infinity, i.e. increase the upper frequency bound until the noise value stops to increase.

Title: Re: MOS aspect retio less than 1
Post by Lex on Apr 10^th, 2012, 12:52am

RobG wrote on Apr 6^th, 2012, 6:08pm:

...

I would expect (but do not know) that dummy devices are especially important for such narrow widths.

Agreed. My advice would be to place dummy transistors of 1 um wide next to them to get a good poly and STI profile. And by construction you don't suffer from WPE.

Title: Re: MOS aspect retio less than 1
Post by RobG on Apr 10^th, 2012, 12:27pm

mixed_signal wrote on Apr 6^th, 2012, 8:12pm:

ms... I think the proper way is to find the noise power density VN2() over the interval that you care about (say 1/(1 year) to 100 MHz) and then multiply by the frequency response (squared) of the sigma-delta, then integrate the product. You'll find the lower bound of integration isn't important after some point so maybe 1/(1 hour) is low enough frequency.

I'm not sure how to get the sigma-delta frequency response in the calculator. Maybe you could do something like VN2()*(sin(f)/f)^2. Alternatively, you could derive what the effective bandwidth is to the first zero, and then just integrate VN2() out to that voltage.

Let me know if you get a definitive answer!
Rob

Title: Re: MOS aspect retio less than 1
Post by aaron_do on Apr 10^th, 2012, 5:29pm

Hi RobG,

Quote:

You'll find the lower bound of integration isn't important after some point so maybe 1/(1 hour) is low enough frequency.

Actually I've always kind of wondered about this point. Is the lower bound set by how long you expect the device to be turned on for?

thanks,
Aaron

Title: Re: MOS aspect retio less than 1
Post by RobG on Apr 10^th, 2012, 6:28pm

aaron_do wrote on Apr 10^th, 2012, 5:29pm:

Actually I've always kind of wondered about this point. Is the lower bound set by how long you expect the device to be turned on for?

Yes, according to my 30 year old Grey/Meyer text anyway: "... the lower limit of the integration must be specified by the period of observation."

The text then gives two examples of lower integration limits on a noise problem for perspective:
1 cycle/day: Vnoise = 1.75 uV
1 cycle/year: Vnoise = 1.90 uV

For fun I tried the age of the universe (1 cycle/13.75 billion years) and came up with 2.4uV. I'd put a large error band around that number though ;D

Title: Re: MOS aspect retio less than 1
Post by mixed_signal on Apr 10^th, 2012, 10:10pm

Thank you all for the suggestions!

I did transient simulation of BJT based bandgap where i applied a fast ramp Vdd (0 to 1.2 v in 50ns). I have designed for PTAT current =150nA @25C. Simulations show that after 50us current in one branch exactly becomes 150n but current in another branch oscillates from 144n to 157n as shown in fig (attached). Is it a stability problem? The opamp loop through stb analysis shows phase margin of 60 degree.

Thanks

Title: Re: MOS aspect retio less than 1
Post by Frank Wiedmann on Apr 11^th, 2012, 12:58am

Your screenshot is not detailed enough for me to be sure, but this could also be trapezoidal ringing, which is a simulation artifact (see http://www.designers-guide.org/Forum/YaBB.pl?num=1101285512).

Title: Re: MOS aspect retio less than 1
Post by Frank Wiedmann on Apr 11^th, 2012, 1:05am

RobG wrote on Apr 10^th, 2012, 6:28pm:

aaron_do wrote on Apr 10^th, 2012, 5:29pm:

Actually I've always kind of wondered about this point. Is the lower bound set by how long you expect the device to be turned on for?

This noise at very low frequencies is often also called drift.

Title: Re: MOS aspect retio less than 1
Post by RobG on Apr 11^th, 2012, 9:32am

mixed_signal... something doesn't add up... one leg can't be oscillating and the other constant as the total current must remain the same (kirkoff's current law).

Someone posted a similar mysterious oscillation a few weeks ago and it turned out to be ringing in the bias current generator, not the opamp.

Title: Re: MOS aspect retio less than 1
Post by mixed_signal on Apr 11^th, 2012, 12:25pm

Hi RobG,
I chose the conservative option in the transient analysis window and it fixed the problem. I think it is a numerical error.

However I am worried of the initial spike. The stb analysis of the loop shows a phase margin of 60 degree and gain margin of 3 db. Is gain margin insufficient?

Thanks

Title: Re: MOS aspect retio less than 1
Post by Frank Wiedmann on Apr 11^th, 2012, 1:39pm

The circuit might not behave in a linear way during the transition, so loop gain theory (which assumes a linear circuit) might not be applicable during this time. This could be an explanation for an overshoot that is higher than predicted by the value of the phase margin.

A phase margin of 60 degrees should be adequate in most cases, 76 degrees are required to have no overshoot of the step response in a second-order system, see for example http://powerelectronics.com/power_systems/simulation_modeling/Transient-response-phase-margin-PET.pdf.

Title: Re: MOS aspect retio less than 1
Post by RobG on Apr 11^th, 2012, 1:50pm

In addition to what Frank said, look at the effect of capacitance on the tail of the diff pair (which can be severely underestimated if you tie the bulk to the source).

Title: Re: MOS aspect retio less than 1
Post by RobG on Apr 11^th, 2012, 2:14pm

Wow, I just saw your ramping 1.2 in 50 nS. Your problem is probably coming from coupling capacitance. E.g. a 5 fF capacitance will produce a 100 nA current spike.

Title: Re: MOS aspect retio less than 1
Post by mixed_signal on Apr 11^th, 2012, 9:35pm

Thank you all for the suggestions!
I have the following doubts:

1. I have 2u/20u transistors (length=20u) to layout for current mirror in IBM 130nm tech. Shall I lay a single transistor of length 20u for that? Laying 2 nos. of 1u/20u makes it excess long and will not be of any matching help. OR
Can i tie 10 nos. of 2u length transistors in series with all gates shorted to get equivalent transistor of length 20u as shown in Bakers book?

2. For real implementation, how much gain margin shall we choose for opamp? Is phase margin of 60 not sufficient ?
In my case i increased the gain margin to 10dB from 3 dB and I have the following transient response. Is the spike acceptable?

Title: Re: MOS aspect retio less than 1
Post by mixed_signal on Apr 19^th, 2012, 7:13pm

Hi,

Pls help :)