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Simulators >> AMS Simulators >> ADE XL create local variable from verilog ams code...
https://designers-guide.org/forum/YaBB.pl?num=1333640782

Message started by nzborsti on Apr 5^th, 2012, 8:46am

Title: ADE XL create local variable from verilog ams code...
Post by nzborsti on Apr 5^th, 2012, 8:46am

Hello to everyone,

I am new to Verilog AMS and Cadence Virtuoso and so I do have quite a few problems to get started. Maybe someone is able to help me with this one:

I wrote a simple verilog ams code for a low pass filter which includes the following line:

parameter real nst_0=1 [0:inf);

I managed to create a schematic and a config file so that I was able to run an ac analysis in ADE XL. Now I want to run the same analysis again but this time I want to have the parameter "nst_0" listed under "local variables" (on the left in the Virtuoso ADE XL window) so that is easy to change the value for this paramter.

I already tried to assign a string " nst" to the value of "nst_0" in the "edit Object Properties" Window. After that I added a Design Variable in the Virtuoso ADE XL window named "nst" and assigned a value to this variable. But this didn't do the job cause everytime I hit the simulate button a error comes up:

ncelab: *E,CUBSPA (./netlist.vams,22|22): Assignment of string to real or integer type parameter.

Another try was to use the "Copy from" button which comes up when you click on "add local variable" but nothing happend.

Has anyone an idea how to get this job done?

Kind regards

Title: Re: ADE XL create local variable from verilog ams code...
Post by ywguo on Apr 13^th, 2012, 8:20am

I stumbled into similar problem not only with ADE-XL, but also with ADE-L. :'(

Title: Re: ADE XL create local variable from verilog ams code...
Post by boe on Apr 16^th, 2012, 8:55am

Hi,
did you search the forum?

- B O E

Title: Re: ADE XL create local variable from verilog ams code...
Post by nzborsti on Apr 20^th, 2012, 6:10am

Hi,
I have been looking quite a while but so far no success. Any one out there who is able to help????
thx

Title: Re: ADE XL create local variable from verilog ams code...
Post by boe on Apr 20^th, 2012, 12:34pm

Hi,
last year, we had a discussion about this here...

- B O E

Title: Re: ADE XL create local variable from verilog ams code...
Post by nzborsti on Apr 23^rd, 2012, 1:56am

Hi,
thank you very much for pointing me in the right direction. But for somereason I couldn't find the right thread. Can you please give me a link....

thx

Title: Re: ADE XL create local variable from verilog ams code...
Post by boe on Apr 23^rd, 2012, 2:33am

Hi,
Searching for the error message CUBSPA finds the thread
http://www.designers-guide.org/Forum/YaBB.pl?num=1297252828.

- B O E

Title: Re: ADE XL create local variable from verilog ams code...
Post by nzborsti on Apr 23^rd, 2012, 2:41am

Hi,
thank you very much for pointing me in the right direction. But for somereason I couldn't find the right thread. Can you please give me a link....

thx

Title: Re: ADE XL create local variable from verilog ams code...
Post by nzborsti on Apr 26^th, 2012, 12:28am

Hi,

thank you BOE for the link, it really helped me a lot to get closer to the solution and now it works -> problem solved.

All I had to do is to use the CDF toll , open each "cell" as "base" and enable the "parse as number" option. After that I could easily add the design variables in ADE XL and had no errors coming up.